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| TOSHIBA TLCS-900 Series CMOS 16-bit Microcontroller TMP96C141AF 1. Outline and Device Characteristics TMP96C141AF The TMP96C141AF is high-speed advanced 16-bit microcontroller developed for controlling medium to large-scale equipment. The TMP96C141AF is housed in an 80-pin flat package. Device characteristics are as follows: (1) Original 16-bit CPU * TLCS-90 instruction mnemonic upward compatible. * 16M-byte linear address space * General-purpose registers and register bank system * 16-bit multiplication/division and bit transfer/arithmetic instructions * High-speed micro DMA - 4 channels (1.6s/2 bytes @ 20MHz) (2) Minimum instruction execution time - 200ns @ 20MHz (3) Internal RAM: 1K byte Internal ROM: None (4) External memory expansion * Can be expanded up to 16M bytes (for both programs and data). * Can mix 8- and 16-bit external data buses. ... Dynamic data bus sizing (5) 8-bit timers: 2 channels (6) 8-bit PWM timers: 2 channels (7) 16-bit timers: 2 channels (8) Pattern generators: 4 bits, 2 channels (9) Serial interface: 2 channels (10) 10-bit A/D converter: 4 channels (11) Watchdog timer (12) Chip select/wait controller: 3 blocks (13) Interrupt functions * 3 CPU interrupts... ...SWI instruction, privileged violation, and Illegal instruction * 14 internal interrupts 7-level priority can be set. * 6 external interrupts (14) I/O ports (15) Standby function : 3 halt modes (RUN, IDLE, STOP) The information contained here is subject to change without notice. The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic equipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equipments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA. TOSHIBA CORPORATION 1 TMP96C141AF Figure 1. TMP96C141AF Block Diagram 2 TOSHIBA CORPORATION TMP96C141AF 2. Pin Assignment and Functions The assignment of input/output pins for TMP96C141AF, their name and outline functions are described below. 2.1 Pin Assignment Figure 2.1 shows pin assignment of TMP96C141AF. Figure 2.1 Pin Assignment (80-pin QFP) TOSHIBA CORPORATION 3 TMP96C141AF 2.2 Pin Names and Functions The names of input/output pins and their functions are described below. Table 2.2. Pin Names and Functions Pin Name P00 ~ P07 AD0 ~ AD7 P10 ~ P17 AD8 ~ AD15 A8 ~ A15 P20 ~ P27 A0 ~ A7 A16 ~ A23 P30 RD P31 WR P32 HWR P33 WAIT P34 BUSRQ P35 BUSAK P36 R/W P37 RAS P40 CS0 CAS0 Note: Number of Pins 8 I/O I/O Tri-state I/O Tri-state Output I/O Output Output Output Output Output Output I/O Output I/O Input I/O Input I/O Output I/O Output I/O Output I/O Output Output Functions Port 0: I/O port that allows I/O to be selected on a bit basis Address / data (lower): 0 - 7 for address / data bus Port 1: I/O port that allows I/O to be selected on a bit basis Address data (upper): 8 - 15 for address / data bus Address: 8 to 15 for address bus Port 2: I/O port that allows selection of I/O on a bit basis (with pull-down resistor) Address: 0 - 7 for address bus Address: 16 - 23 for address bus Port 30: Output port Read: Strobe signal for reading external memory Port 31: Output port Write: Strobe signal for writing data on pins AD0 -7 Port 32: I/O port (with pull-up resistor) High write: Strobe signal for writing data on pins AD8 - 15 Port 33: I/O port (with pull-up resistor) Wait: Pin used to request CPU bus wait Port 34: I/O port (with pull-up resistor) Bus request: Signal used to request high impedance for AD0 - 15, A0 - 23, RD, WR, HWR, R/W, RAS, CS0, CS1, and CS2 pins. (For external DMAC) Port 35: I/O (with pull-up resistor) Bus acknowledge: Signal indicating that AD0 - 15, A0 - 23, RD, WR, HWR, R/W, RAS, CS0, CS1, and CS2 pins are at high impedance after receiving BUSRQ. (For external DMAC) Port 36: I/O port (with pull-up resistor) Read/write: 1 represents read or dummy cycle; 0, write cycle. Port 37: I/O port (with pull-up resistor) Row address strobe: Outputs RAS strobe for DRAM. Port 40: I/O port (with pull-up resistor) Chip select 0: Outputs 0 when address is within specified address area. Column address strobe 0: Outputs CAS strobe for DRAM when address is within specified address area. 8 8 1 1 1 1 1 1 1 1 1 With the external DMA controller, this device's built-in memory or built-in I/O cannot be accessed using the BUSRQ and BUSAK pins. 4 TOSHIBA CORPORATION TMP96C141AF Pin Name P41 CS1 CAS1 P42 CS2 CAS2 P50 ~ P53 AN0 ~ AN3 VREF AGND P60 ~ P63 PG00 ~ PG03 P64 ~ P67 PG10 ~ PG13 P70 T10 P71 T01 P72 T02 P73 T03 P80 TI4 INT4 P81 TI5 INT5 P82 TO4 P83 TO5 Number of Pins 1 I/O I/O Output Output I/O Output Output Input Input Input Input I/O Output I/O Output I/O Input I/O Output I/O Output I/O Output I/O Input Input I/O Input Input I/O Output I/O Output Functions Port 41: I/O port (with pull-up resistor) Chip select 1: Outputs 0 if address is within specified address area. Column address strobe 1: Outputs CAS strobe for DRAM if address is within specified address area. Port 42: I/O port (with pull-up resistor) Chip select 2: Outputs 0 if address is within specified address area. Column address strobe 2: Outputs CAS strobe for DRAM if address is within specified address area. Port 5: Input port Analog input: Input to A/D converter Pin for reference voltage input to A/D converter Ground pin for A/D converter Ports 60 - 63: I/O ports that allow selection of I/O on a bit basis (with pull-up resistor) Pattern generator ports: 00 - 03 Ports 64 - 67: I/O ports that allow selection of I/O on a bit basis (with pull-up resistor) Pattern generator ports: 10 - 13 Port 70: I/O port (with pull-up resistor) Timer input 0: Timer 0 input Port 71: I/O port (with pull-up resistor) Timer output 1: Timer 0 or 1 output Port 72: I/O port (with pull-up resistor) PWM output 2: 8-bit PWM timer 2 output Port 73: I/O port (with pull-up resistor) PWM output 3: 8-bit PWM timer 3 output Port 80: I/O port (with pull-up resistor) Timer input 4: Timer 4 count/capture trigger signal input Interrupt request pin 4: Interrupt request pin with programmable rising/falling edge Port 81: I/O port (with pull-up resistor) Timer input 5: Timer 4 count/capture trigger signal input Interrupt request pin 5: Interrupt request pin with rising edge Port 82: I/O port (with pull-up resistor) Timer output 4: Timer 4 output pin Port 83: I/O port (with pull-up resistor) Timer output 5: Timer 4 output pin 1 4 1 1 4 4 1 1 1 1 1 1 1 1 TOSHIBA CORPORATION 5 TMP96C141AF Pin Name P84 TI6 INT6 P85 TI7 INT7 P86 TO6 P87 INT0 P90 TXD0 P91 RXD0 P92 CTS0 P93 TXD1 P94 RXD1 P95 SCLK1 WDTOUT NMI CLK EA ALE RESET X1/X2 VCC VSS Note: Number of Pins 1 I/O I/O Input Input I/O Input Input I/O Output I/O Input I/O Output I/O Input I/O Input I/O Output I/O Input I/O I/O Output Input Output Input Output Input I/O Functions Port 84: I/O port (with pull-up resistor) Timer input 6: Timer 5 count/capture trigger signal input Interrupt request pin 6: Interrupt request pin with programmable rising/falling edge Port 85: I/O port (with pull-up resistor) Timer input 7: Timer 5 count/capture trigger signal input Interrupt request pin 7: Interrupt request pin with rising edge Port 86: I/O port (with pull-up resistor) Timer output 6: Timer 5 output pin Port 87: I/O port (with pull-up resistor) Interrupt request pin 0: Interrupt request pin with programmable level/rising edge Port 90: I/O port (with pull-up resistor) Serial send data 0 Port 91: I/O port (with pull-up resistor) Serial receive data 0 Port 92: I/O port (with pull-up resistor) Serial data send enable 0 (Clear to Send) Port 93: I/O port (with pull-up resistor) Serial send data 1 Port 94: I/O port (with pull-up resistor) Serial receive data 1 Port 95: I/O port (with pull-up resistor) Serial clock I/O 1 Watchdog timer output pin Non-maskable interrupt request pin: Interrupt request pin with falling edge. Can also be operated at rising edge by program. Clock output: Outputs X1 / 4 clock. Pulled-up during reset. External access: 0 should be inputted with TMP96C141AF 1, with TMP96CM40F/TMP96PM40F. Address latch enable Reset: Initializes LSI. (With pull-up resistor) Oscillator connecting pin Power supply pin (+ 5V) GND pin (0V) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 Pull-up/pull-down resistor can be released from the pin by software. 6 TOSHIBA CORPORATION TMP96C141AF 3. Operation This section describes in blocks the functions and basic operations of the TMP96C141AF device. Check the chapter Guidelines and Restrictions for proper care of the device. 3.1 CPU The TMP96C141AF device has a built-in high-performance 16-bit CPU. (For CPU operation, see TLCS-900 CPU in the book Core Manual Architecture User Manual.) This section describes CPU functions unique to TMP96C141AF that are not described in that manual. 3.1.1 Reset To reset the TMP96C141AF, the RESET input must be kept at 0 for at least 10 system clocks (10 states: 1s with a 20MHz system clock) within an operating voltage range and with a stable oscillation. When reset is accepted, the CPU sets as follows: * Program counter (PC) to 8000H. * Stack pointer (XSP) for system mode to 100H. * SYSM bit of status register (SR) to 1. (Sets to system mode.) * IFF2 to 0 bits of status register to 111. (Sets mask register to interrupt level 7.) * MAX bit of status register to 0. (Sets to minimum mode.) * Bits RFP2 to 0 of status register to 000. (Sets register banks to 0.) When reset is released, instruction execution starts from address 8000H. CPU internal registers other than the above are not changed. When reset is accepted, processing for built-in I/Os, ports, and other pins is as follows: * Initializes built-in I/O registers as per specifications. * Sets port pins (including pins also used as built-in I/Os) to general-purpose input/output port mode (sets I/O ports to input ports). * Sets the WDTOUT pin to 0. (Watchdog timer is set to enable after reset.) * Pulls up the CLK pin to 1. * Sets the ALE pin to 0. TOSHIBA CORPORATION 7 TMP96C141AF 3.2 Memory Map Figure 3.2 is a memory map of the TMP96C141AF. Figure 3.2 Memory Map 8 TOSHIBA CORPORATION TMP96C141AF 3.3 Interrupts The TLCS-900 interrupts are controlled by the CPU interrupt mask flip-flop (IFF2 to 0) and the built-in interrupt controller. The TMP96C141AF have altogether the following 23 interrupt sources: A fixed individual interrupt vector number is assigned to each interrupt source; six levels of priority (variable) can also be assigned to each maskable interrupt. Non-maskable interrupts have a fixed priority of 7. When an interrupt is generated, the interrupt controller * Interrupts from the CPU...3 (Software interrupts, privileged violations, and Illegal (undefined) instruction execution) * Interrupts from external pins (NMI, INT0, and INT4 to 7)...6 * Interrupts from built-in I/Os...14 sends the value of the priority of the interrupt source to the CPU. When more than one interrupt is generated simultaneously, the interrupt controller sends the value of the highest priority (7 for non-maskable interrupts is the highest) to the CPU. The CPU compares the value of the priority sent with the value in the CPU interrupt mask register (IFF2 to 0). If the value is greater than that of the CPU interrupt mask register, the interrupt is accepted. The value in the CPU interrupt mask register (IFF2 to 0) can be changed using the EI instruction (contents of the EI num/IFF<2:0> = num). For example, programming EI 3 enables acceptance of maskable interrupts with a priority of 3 or greater, and non-maskable interrupts which are set in the interrupt controller. The DI instruction (IFF<2:0> = 7) operates in the same way as the EI 7 instruction. Since the priority values for maskable interrupts are 0 to 6, the DI instruction is used to disable maskable interrupts to be accepted. The EI instruction becomes effective immediately after execution. (With the TLCS-90, the EI instruction becomes effective after execution of the subsequent instruction.) In addition to the general-purpose interrupt processing mode described above, there is also a high-speed micro DMA processing mode. High-speed micro DMA is a mode used by the CPU to automatically transfer byte or word data. It enables the CPU to process interrupts such as data saves to built-in I/Os at high speed. Figure 3.3 (1) is a flowchart showing overall interrupt processing. TOSHIBA CORPORATION 9 TMP96C141AF Figure 3.3 (1) Interrupt Processing Flowchart 10 TOSHIBA CORPORATION TMP96C141AF 3.3.1 General-Purpose Interrupt Processing When accepting an interrupt, the CPU operates as follows: (1) The CPU reads the interrupt vector from the interrupt controller. When more than one interrupt with the same level is generated simultaneously, the interrupt controller generates interrupt vectors in accordance with the default priority (which is fixed as follows: the smaller the vector value, the higher the priority), then clears the interrupt request. (2) The CPU pushes the program counter and the status register to the system stack area (area indicated by the system mode stack pointer). (3) The CPU sets a value in the CPU interrupt mask register Bus Width of Stack Area 8 bit 16 bit Interrupt Processing State Number MAX mode 23 17 Min mode 19 15 To return to the main routine after completion of the interrupt processing, the RETI instruction is usually used. Executing this instruction restores the contents of the program counter and the status registers. Though acceptance of non-maskable interrupts cannot be disabled by program, acceptance of maskable interrupts can. A priority can be set for each source of maskable interrupts. The CPU accepts an interrupt request with a priority higher than the value in the CPU mask register TOSHIBA CORPORATION 11 TMP96C141AF Table 3.3 (1) TMP96C141AF Interrupt Table Default Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 - - - Maskable NonMaskable Type Reset INTPREV: INTUNDEF: SWI 3 Instruction SWI 4 Instruction SWI 5 Instruction SWI 6 Instruction SWI 7 Instruction NMI Pin INTWD: INTO pin INT4 pin INT5 pin INT6 pin INT7 pin (Reserved) INTT0: INTT1: INTT2: INTT3: INTTR4: INTTR5: INTTR6: INTTR7: INTRX0: INTTX0: INTRX1: INTTX1: INTAD: (Reserved) (Reserved) (Reserved) 8-bit timer 0 8-bit timer 1 8-bit timer 2/PWM0 8-bit timer 3/PWM1 16-bit timer 4 (TREG4) 16-bit timer 4 (TREG5) 16-bit timer 5 (TREG6) 16-bit timer 5 (TREG7) Serial receive (Channel.0) Serial send (Channel.0) Serial receive (Channel.1) Serial send (Channel.1) A / D conversion completion Watchdog timer Interrupt Source , or SW10 instruction Privileged violation, or SWI1 Illegal instruction, or SWI2 Vector Value "V" 0000H 0010H 0020H 0030H 0040H 0050H 0060H 0070H 0080H 0090H 00A0H 00B0H 00C0H 00D0H 00E0H 00F0H 0100H 0110H 0120H 0130H 0140H 0150H 0160H 0170H 0180H 0190H 01A0H 01B0H 01 C0H 01D0H 01E0H 01F0H Start Address 8000H 8010H 8020H 8030H 8040H 8050H 8060H 8070H 8080H 8090H 80A0H 80B0H 80C0H 80D0H 80E0H 80F0H 8100H 8110H 8120H 8130H 8140H 8150H 8160H 8170H 8180H 8190H 81A0H 81B0H 81C0H 81D0H 81E0H 81F0H High-Speed Micro DMA Start Vector - - - - - - - - 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 3.3.2 High-Speed Micro DMA In addition to the conventional interrupt processing, the TLCS900 also has a high-speed micro DMA function. When an interrupt is accepted, in addition to an interrupt vector, the CPU receives data indicating whether processing is high-speed micro DMA mode or general-purpose interrupt. If high-speed micro DMA mode is requested, the CPU performs high-speed micro DMA processing. The TLCS-900 can process at very high speed compared with the TLCS-90 micro DMA because it has transfer parameters in dedicated registers in the CPU. Since those dedicated registers are assigned as CPU control registers, they can only be accessed by the LDC (privileged) instruction. 12 TOSHIBA CORPORATION TMP96C141AF (1) High-Speed Micro DMA Operation High-speed micro DMA operation starts when the accepted interrupt vector value matches the micro DMA start vector value set in the interrupt controller. The high-speed micro DMA has four channels so that it can be set for up to four types of interrupt source. When a high-speed micro DMA interrupt is accepted, data is automatically transferred from the transfer source address to the transfer destination address set in the control register, and the transfer counter is decremented. If the value in the counter after decrementing is other than 0, high-speed micro DMA processing is completed. If the value in the counter after decrementing is 0, general-purpose interrupt processing is performed. In read-only mode, which is provided for DRAM refresh, the value in the counter is ignored and dummy read is repeated. The 32-bit control registers are used for setting transfer source/destination addresses. However, the TLCS-900 has only 24 address pins for output. A 16M-byte space is available for the high-speed micro DMA. Also in normal mode operation, the all address space (in other words, the space for system mode which is set by the CS/WAIT controller) can be accessed by high-speed micro DMA processing. There are two data transfer modes: one-byte mode and one-word mode. Incrementing, decrementing, and fixing the transfer source/destination address after transfer can be done in both modes. Therefore data can easily be transferred betweenI/O and memory and between I/Os. For details of transfer modes, see the description of transfer mode registers. The transfer counter has 16 bits, so up to 65536 transfers (the maximum when the initial value of the transfer counter is 0000H) can be performed for one interrupt source by highspeed micro DMA processing. A the data transferred by the DMA function, the transfer nter was decreased. When this counter is "0"H, the processor operates general interrupt processing. At this time if the same channel of interrupt is required next interrupt, the transfer counter starts from 65536. Interrupt sources processed by high-speed micro DMA processing are those with the high-speed micro DMA start vectors listed in Table 3.3 (1). TOSHIBA CORPORATION 13 TMP96C141AF The following timing chart is a high-speed DMA cycle of the Transfer Address Increment mode (the other mode execept the Read-only mode is same as this) (Condition: MIN mode, 16bit Bus width for 16M Byte, 0 wait) (2) Register Configuration (CPU Control Register) These Control Registers cannot be set only "LCD cr, r" instruction. 14 TOSHIBA CORPORATION TMP96C141AF (3) Transfer Mode Register Details This condition is 16-bit bus width and 0 wait of source/destination address space. Note: n: corresponds to high-speed DMA channels 0 - 3. DMADn +/DMASn + : Post-increment (Increments register value after transfer.) DMADn -/DMASn - : Post-decrement (Decrement register value after transfer.) All address space (the space for system mode) can be accessed by high-speed DMA. Do not use undefined codes for transfer mode control. TOSHIBA CORPORATION 15 TMP96C141AF ... ity setting register, and a register for storing the high-speed micro DMA start vector. The interrupt request flip-flop is used to latch interrupt requests from peripheral devices. The flip-flop is cleared to 0 at reset, when the CPU reads the interrupt channel vector after the acceptance of interrupt, or when the CPU executes an instruction that clears the interrupt of that channel (writes 0 in the clear bit of the interrupt priority setting register). For example, to clear the INT0 interrupt request, set the register after the DI instruction as follows. Zero-clears the INT0 Flip-Flop. mapping start address A read only mode (for DRAM refresh) ... Timer Setting Set the timers so that interrupts are generated at intervals of 62.5s or less. Interrupt controller setting Set the timer interrupt mask h other interrupt mask. Write the above timer interrupt vector value in the High-Speed DMA start vector register, DMA0V. (Operation description) The DRAM data bus is an 8-bit bus and the micro DMA is in read-only mode (4 bytes), so refresh is performed four times per interrupt. When a 512 refresh/8ms DRAM is connected, DRAM refresh is performed sufficiently if the micro DMA is started every 15.625s x 4 = 62.4s or less, since the timing is 15.625s/refresh. (Overhead) Each processing time by the micro DMA is 1.8s (18 states) @ 20MHz with an 8-bit data bus. In the above example, the micro DMA is started every 62.5s, 1.8s/62.5s = 0.029; thus, the overhead is 2.9%. 3.3.3 Interrupt Controller Figure 3.3.3 (1) is a block diagram of the interrupt circuits. The left half of the diagram shows the interrupt controller; the right half includes the CPU interrupt request signal circuit and the HALT release signal circuit. Each interrupt channel (total of 20 channels) in the interrupt controller has an interrupt request flip-flop, interrupt prior- The status of the interrupt request flip-flop is detected by reading the clear bit. Detects whether there is an interrupt request for an interrupt channel. The interrupt priority can be set by writing the priority in the interrupt priority setting register (e.g., INTE0AD, INTE45, etc.) provided for each interrupt source. Interrupt levels to be set are from 1 to 6. Writing 0 or 7 as the interrupt priority disables the corresponding interrupt request. The priority of the non-maskable interrupt (NMI pin, watchdog timer, etc.) is fixed to 7. If interrupt requests with the same interrupt level are generated simultaneously, interrupts are accepted in accordance with the default priority (the smaller the vector value, the higher the priority). The interrupt controller sends the interrupt request with the highest priority among the simultaneous interrupts and its vector address to the CPU. The CPU compares the priority value 16 TOSHIBA CORPORATION TMP96C141AF Figure 3.3.3 (1) Block Diagram of Interrupt Controller TOSHIBA CORPORATION 17 TMP96C141AF (1) Interrupt Priority Setting Register 18 TOSHIBA CORPORATION TMP96C141AF (2) External Interrupt Control TOSHIBA CORPORATION 19 TMP96C141AF (3) High-Speed Micro DMA Start Vector When the CPU reads the interrupt vector after accepting an interrupt, it simultaneously compares the interrupt vector with each channel's micro DMA start vector (bits 4 to 8 of the interrupt vector). When both match, the interrupt is processed in micro DMA mode for the channel whose value matched. If the interrupt vector matches more than one channel, the channel with the lower channel number has a higher priority. (read-modify-write is not possible.) Micro DMA0 Start Vector 7 6 5 4 DMA0V8 0 3 DMA0V7 0 2 1 DMA0V5 0 0 DMA0V4 0 DMA0V (007CH) bit Symbol Read / Write After reset DMA0V6 W 0 Micro DMA1 Start Vector 7 6 5 4 DMA1V8 0 3 DMA1V7 0 2 (read-modify-write is not possible.) 1 DMA1V5 0 0 DMA1V4 0 DMA1V (007DH) bit Symbol Read / Write After reset DMA1V6 W 0 Micro DMA2 Start Vector 7 6 5 4 DMA2V8 0 3 DMA2V7 0 2 (read-modify-write is not possible.) 1 DMA2V5 0 0 DMA2V4 0 DMA2V (007EH) bit Symbol Read / Write After reset DMA2V6 W 0 Micro DMA3 Start Vector 7 6 5 4 DMA3V8 0 3 DMA3V7 0 2 (read-modify-write is not possible.) 1 DMA3V5 0 0 DMA3V4 0 DMA3V (007FH) bit Symbol Read / Write After reset DMA3V6 W 0 (4) Notes The instruction execution unit and the bus interface unit of this CPU operate independently of each other. Therefore, if the instruction used to clear an interrupt request flag of an interrupt is fetched before the interrupt is generated, it is possible that the CPU might execute the fetched instruction to clear the interrupt request flag while reading the interrupt vector after accepting the interrupt. If so, the CPU would read the default vector 00A0H and start the interrupt processing from the address 80A0H. To avoid this, make sure that the instruction used to clear the interrupt request flag comes after the DI instruction. 20 TOSHIBA CORPORATION TMP96C141AF 3.4 Standby Function When the HALT instruction is executed, the TMP96C141AF enters RUN, IDLE, or STOP mode depending on the contents of the HALT mode setting register. (3) STOP (1) RUN : Only the CPU halts; power consumption remains unchanged. : Only the built-in oscillator operates, while all other built-in circuits halt. Power consumption is reduced to 1/10 or less than that during normal operation. : All internal circuits including the built-in oscillator halt. This greatly reduces power consumption. The states of the port pins in STOP mode can be set as listed in Table 3.4 (1) using the I/O register WDMOD (2) IDLE 7 6 WDTP1 0 00 : 2 / fc 01 : 2 18 / fc 10 : 220/ fc 11 : 222/ fc Detection time 16 5 WDTP0 0 4 WARM R/W 0 Warming up time 0 : 216 /fc 1 : 218 /fc 3 HALTM1 0 Standby mode 00 : RUN 01 : STOP 10 : IDLE 11 : Don't care 2 HALTM0 0 mode mode mode 1 RESCR 0 1: Connects watchdog timer output to RESET pin internally. 0 DRVE 0 1: Drive pin even in STOP mode. WDMOD (005CH) Read/Write After reset Bit Symbol WDTE 1 1 : WDT Enable Function When STOP mode is released by other than a reset, the system clock output starts after allowing some time for warming up set by the warming-up counter fro stabilizing the bulit-in oscillator. To release STOP mode by reset, it is necessary to allow the oscillator to stabilize. To release standby mode, a reset or an interrupt is used. To release IDLE or STOP mode, only an interrupt by the NMI or INT0 pin, or a reset can be used. The details are described below: Standby Release by Interrupt Interrupt Level Standby Mode RUN IDLE STOP Interrupt Mask (IFF2 to 0) Interrupt Request Level Can be released by any interrupt. After standby mode is released, interrupt processing starts. Can only be released by NMI or INT0 pin. After standby mode is released, interrupt processing starts. (Note) Interrupt Mask (IFF2 to 0) > Interrupt Request Level Can only be released by INT0 pin. Processing resumes from address next to HALT instruction. TOSHIBA CORPORATION 21 TMP96C141AF Table 3. 4 (1) Pin States in STOP Mode 96C141AF Pin Name Input mode/AD0 ~ 7 Output mode Input mode/AD8 ~ 15 Output mode/A8 ~ 15 Input mode Output mode/A0 ~ 7, A16 ~ 23 Output Input mode Output mode Input mode Output mode Input mode Output mode Input Input mode Output mode Input mode Output mode Input mode Output mode Input mode Output mode Input mode Output mode Input Output Output Output Input Input Input Output I/O DRVE = 0 P0 P1 P2 P30 (RD), P31 (WR) P32 ~ P37 P40, P41 P42 (CS2/CAS2) P5 P6 P7 P80 ~ P86 P87 (INT0) P9 NMI WDTOUT ALE CLK RESET EA X1 X2 -: Input: Input: Output: PU: PD: *: x: Note: 96CM40/96PM40 DRVE = 1 - x - x PD* Output "1" Output PU Output PU Output PD Output - PU Output PU Output PU Output PU Output PU Output Input Output "0" "1" Input Input - "1" DRVE = 0 - - - - PD* PD* - DRVE = 1 - Output - Output PD* Output Output - x - x PD* PD* - PU PU PU* PU* PD* PD* - PU* PU* PU* PU* PU* PU* PU PU PU* PU* Input Output "0" - Input Input - "1" Input for input mode/input pin is invalid; output mode/output pin is at high impedance. Input enable state Input gate in operation. Fix input voltage to 0 or 1 so that input pin stays constant. Output state Programmable pull-up pin. Fix the pin to avoid through current since the input gate operates when a pull-up resistor is not set. Programmable pull-down pin. Fix the pin like a pull-up pin when a pull-down resistor is not set. Input gate disable state. No through current even if the pin is set to high impedance. Cannot set. Port registers are used for controlling programmable pull-up/pull-down. If a pin is also used for an output function (e.g., TO1) and the output function is specified, whether pull-up or pull-down is selected depends on the output function data. If a pin is also used for an input function, whether pull-up or pull-down is selected depends on the port register setting value only. 22 TOSHIBA CORPORATION TMP96C141AF 3.5 Functions of Ports The TMP96CM40F/TMP96PM40F has 65 bits for I/O ports. The TMP96C141AF, TMP96C041AF has 47 bits for I/O ports because Port0, Port1, P30, and P31 are dedicated pins for AD0 to 7, AD8 to 15, RD, and WR. These port pins have I/O functions for the built-in CPU and internal I/Os as well as general-purpose I/O port functions. Table 3.5 lists the function of each port pin. (R: = With programmable pull-up resistor = WIth programmable pull-down Table 3.5 Functions of Ports Port Name Port0 Port1 Port2 Port 3 Pin Name P00 ~ P07 P10 ~ P17 P20 ~ P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 P41 P42 P50 ~ P53 P60 ~ P67 P70 P71 P72 P73 P80 P81 P82 P83 P84 P85 P86 P87 P90 P91 P92 P93 P94 P95 Number of Pins 8 8 8 1 1 1 1 1 1 1 1 1 1 1 4 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Direction I/O I/O I/O Output Output I/O I/O I/O I/O I/O I/O I/O I/O I/O Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O R - - - - - Direction Setting Unit Bit Bit Bit (Fixed) (Fixed) Bit Bit Bit Bit Bit Bit Bit Bit Bit (Fixed) Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Pin Name for Built-in Function AD0 ~ AD7 AD8 ~ AD15/ A8 ~ A15 A0 ~ A7/ A16 ~ A23 RD WR HWR WAIT BUSRQ BUSAK R/W RAS CS0 / CAS0 CS1 / CAS1 CS2 / CAS2 AN0 ~ AN3 PG00 ~ PG03, PG10 ~ PG13 T10 TO1 TO2 TO3 T14/INT4 T15/INT5 TO4 TO5 T16 / INT6 T17 / INT7 TO6 INT0 TXD0 RXD0 CTS0 TXD1 RXD1 SCLK1 Port4 Port5 Port6 Port7 Port8 Port9 TOSHIBA CORPORATION 23 TMP96C141AF Resetting makes the port pins listed below function as general-purpose I/O ports. I/O pins programmable for input or output function as input ports. To set port pins for built-in functions, a program is required. Since the TMP96C141AF has an external ROM, some ports are permanently assigned to the CPU. P00 ~ P07 AD0 ~ AD7 P10 ~ P17 AD8 ~ AD15 P30 RD P31 WR Bus release function The TMP96C141AF has the internal pull-up and pulldown resistors to fix the bus control signals at bus release. Table 3.5 (1) shows the pin condition at bus release (BUSAK) = "L"). * * * * Pin state at bus release Pin Name Port mode P00 - P07 (AD0 - AD7) P10 - P17 (AD8 - AD15) P30 (RD) P31 (WR) P32 (HWR) P37 (RAS) P36 (R/W) P40 (CS0/CAS0) P41 (CS1/CAS1) P42 (CS2/CAS2) P20 - P27 (A16 - A23) P42 (CS2/CAS2) Function mode No status change (these pins are not "Hz") These pins are "Hz". These pins are "Hz". ("Hz" status after these pins are driven to high level.) The output buffer is "OFF" after these pins are drinen high. These pins are added in the internal resistor of pull-up. It's no relation for the value of output latch. (*) The output buffer is "OFF" after these pins are drinen high. These pins are added in the internal resistor of pull-down. It's no relation for the value of output latch. (*) P42 has the resistor of programmable pull-down, but when the bus are released, P42 pin is added a resistor of pullup. That is, when it is used for bus release (BUSAK = "0"), the pins of below need pull-up or pull-down resistor for an external circuit. P00 - P07 (AD07) P10 - P17 (AD8 - AD15) P30 (RD) P31 (WR) When the bus is released, both internal memory and internal I/O cannot be accessed. But the internal I/O continues to run. Therefore, be careful about releasing time and set the setection time WDT. Figure 3.5. Example of external bus interface using bus release function. 24 TOSHIBA CORPORATION TMP96C141AF 3.5.1 Port 0 (P00 - P07) Port 0 is an 8-bit general-purpose I/O port. I/O can be set on a bit basis using control register P0CR to 0 and sets Port 0 to input mode. In addition to functioning as a general purpose I/O port, Port 0 also functions as an address data bus (AD0 to 7). To access external memory, Port 0 functions as an address data bus (AD 0 to 7) and all bits of the control register P0CR are cleared to 0. With the TMP96C141AF/TMP96C041AF, which comes with an external ROM, Port 0 always functions as an address data bus (AD0 to 7) regardless of the value set in control register P0CR. 3.5.2 Port 1 (P10 - P17) Port 1 is an 8-bit general-purpose I/O port. I/O can be set on a bit basis using control register P1CR and function register P1FC. Resetting resets all bits of output latch P1, control register P1CR, and function register P1FC to 0 and sets Port 1 to input mode. In addition to functioning as a general purpose I/O port, Port 1 also functions as an address data bus (AD8 to 15) or an address bus (A8 to 15). With the TMP96C141AF/TMP96C041AF, which comes with an external ROM, Port 1 always functions as an address data bus (AD8 to 15) regardless of the value set in control register P1CR. Figure 3.5 (1). Port 0 Figure 3.5 (2). Port 1 TOSHIBA CORPORATION 25 TMP96C141AF Port 0 Register Figure 3.5 (3). Registers for Ports 0 and 1 26 TOSHIBA CORPORATION TMP96C141AF 3.5.3 Port 2 (P20 - P27) Port 2 is an 8-bit general-purpose I/O port. I/O can be set on bit basis using the control register P2CR and function register P2FC. Resetting resets all bits of output latch P2, control register P2CR and function register P2FC to 0. It also sets Port 2 to input mode and connects a pull-down resistor. To disconnect the pull-down resistor, write 1 in the output latch. In addition to functioning as a general-purpose I/O port, Port 2 also functions as an address data bus (A0 to 7) and an address bus (A16 to 23). Figure 3.5 (4). Port 2 TOSHIBA CORPORATION 27 TMP96C141AF Figure 3.5 (5). Registers for Port 2 28 TOSHIBA CORPORATION TMP96C141AF 3.5.4 Port 3 (P30 - P37) Port 3 is an 8-bit general-purpose I/O port. I/O can be set on a bit basis, but note that P30 and P31 are used for output only. I/O is set using control register P3CR and function register P3FC. Resetting resets all bits of output latch P3, control register P3CR (bits 0 and 1 are unused), and function register P3FC to 0. Resetting also outputs 1 from P30 and P31, sets P32 to P37 to input mode, and connects a pullup resistor. In addition to functioning as a general-purpose I/O port, Port 3 also functions as an I/O for the CPU's control/status signal. With the TMP96C141AF, when P30 pin is defined as RD signal output mode ( TOSHIBA CORPORATION 29 TMP96C141AF Figure 3.5 (6). Port 3 (P30, P31, P32, P35, P36, P37) 30 TOSHIBA CORPORATION TMP96C141AF Figure 3.5 (7). Port 3 (P33, P34) TOSHIBA CORPORATION 31 TMP96C141AF Port 3 Register Note: When P33/WAIT pin is used as a WAIT pin, set P#CR Figure 3.5 (8). Registers for Port 3 32 TOSHIBA CORPORATION TMP96C141AF 3.5.5 Port 4 (P40 - P42) Port 4 is a 3-bit general-purpose I/O port. I/O can be set on a bit basis using control register P4CR and function register P4FC. Resetting does the following: - Sets the P40 and P42 output latch registers to 1. - Resets all bits of the P42 output latch register, the control register P4CR, and the function register P4FC to 0. - Sets P40 and P41 to input mode and connects a pull-up resistor. - Sets P42 to input mode and connects a pull-down resistor. In addition to functioning as a general-purpose I/O port, Port 4 also functions as a chip select output signal (CS0 to CS2 or CAS0 to CAS2). TOSHIBA CORPORATION 33 TMP96C141AF Figure 3.5 (9). Port 4 34 TOSHIBA CORPORATION TMP96C141AF Port 4 Register Note: To output chip select signal (CS0/CAS0 to CS2/CAS2), set the corresponding bits of the control register P4CR and the function register to P4FC. The BOCS, B1CS, and B2CS registers of the chip select/wait controller are used to select the CS/CAS function. Figure 3.5 (10). Registers for Port 4 TOSHIBA CORPORATION 35 TMP96C141AF 3.5.6 Port 5 (P50 - P53) Port 5 is a 4-bit input port, also used as an analog input pin. Figure 3.5 (11). Port 5 Port 5 Register 7 P5 (000DH) bit Symbol Read/Write After reset 6 5 4 3 P53 2 P52 R Input mode 1 P51 0 P50 Note: The input channel selection of A/D Converter is set by A/D Converter mode register ADMOD2. Figure 3.5 (12). Registers for Port 5 36 TOSHIBA CORPORATION TMP96C141AF 3.5.7 Port 6 (P60 - P67) Port 6 is an 8-bit general-purpose I/O port. I/O can be set on bit basis. Resetting sets Port 6 as an input port and connects a pull-up resistor. It also sets all bits of the output latch to 1. In addition to functioning as a general-purpose I/O port, Port 6 also functions as a pattern generator PG0/PG1 output. PG0 is assigned to P60 to P63; PG1, to P64 to P67. Writing 1 in the corresponding bit of the port 6 function register (P6FC) enables PG output. Resetting resets the function register P6FC value to 0, and sets all bits to ports. Figure 3.5 (13). Port 6 TOSHIBA CORPORATION 37 TMP96C141AF Port 6 Register Figure 3.5 (14). Registers for Port 6 38 TOSHIBA CORPORATION TMP96C141AF 3.5.8 Port 7 (P70 - P73) Port 7 is a 4-bit general-purpose I/O port. I/O can be set on bit basis. Resetting sets Port 7 as an input port and connects a pull-up resistor. In addition to functioning as a general-purpose I/O port, Port 70 also functions as an input clock pin TI0; Port 71 as an 8-bit timer output (TO1), Port 72 as a PWM0 output (TO2), and Port 73 as a PWM1 output (TO3) pin. Writing 1 in the corresponding bit of the Port 7 function register (P7FC) enables output of the timer. Resetting resets the function register P7FC value to 0, and sets all bits to ports. Figure 3.5 (15). Port 7 TOSHIBA CORPORATION 39 TMP96C141AF Figure 3.5 (16). Registers for Port 7 40 TOSHIBA CORPORATION TMP96C141AF 3.5.9 Port 8 (P80 - P83) Port 8 is an 8-bit general-purpose I/O port. I/O can be set on a bit basis. Resetting sets Port 8 as an input port and connects a pull-up resistor. It also sets all bits of the output latch register P8 to 1. In addition to functioning as a general-purpose I/O port, Port 8 also functions as an input for 16-bit timer 4 and 5 clocks, an output for 16-bit timer F/F 4, 5 and 6 output, and an input for INT0. Writing 1 in the corresponding bit of the Port 8 function register (P8FC) enables those functions. Resetting resets the function register P8FC value to 0, and sets all bits to ports. (1) P80 ~ P86 Figure 3.5 (17). Port 8 (P80 - P86) TOSHIBA CORPORATION 41 TMP96C141AF (2) P87 (INT0) Port 87 is a general-purpose I/O port, and also used as an INT0 pin for external interrupt request input. Figure 3.5 (18). Port 87 42 TOSHIBA CORPORATION TMP96C141AF Figure 3.5 (19). Registers for Port 8 TOSHIBA CORPORATION 43 TMP96C141AF 3.5.10 Port 9 (P90 - P95) Port 9 is a 6-bit general-purpose I/O port. I/Os can be set on a bit basis. Resetting sets Port 9 to an input port and connects a pull-up resistor. It also sets all bits of the output latch register to 1. In addition to functioning as a general-purpose I/O port, Port 9 can also function as an I/O for serial channels 0 and 1. Writing 1 in the corresponding bit of the port 9 function register (P9FC) enables this function. Resetting resets the function register value to 0 and sets all bits to ports. (1) Port 90 and 93 (TXD0/TXD1) Ports 90 and 93 also function as serial channel TXD output pins in addition to I/O ports. They have a programmable open drain function. Figure 3.5 (20). Ports 90 and 93 44 TOSHIBA CORPORATION TMP96C141AF (2) Ports 91 and 94 (RXD0, 1) Ports 91 and 94 are I/O ports, and also used as RXD input pins for serial channels. Figure 3.5 (21). Ports 91 and 94 (3) Port 92 (CTS/SCKL0) Port 92 is an I/O port. It is also used as a CTS input pin for serial channel0; additionally, the CTS0 pin, and also as a SCKL0 I/O pin. Figure 3.5 (22). Port 92 TOSHIBA CORPORATION 45 TMP96C141AF (4) Port 95 (SCLK) Port 95 is a general-purpose I/O port. It is also used as an SCLK I/O pin for serial channel 1. Figure 3.5 (23). Port 95 46 TOSHIBA CORPORATION TMP96C141AF Figure 3.5 (24). Registers for Port 9 TOSHIBA CORPORATION 47 TMP96C141AF 3.6 Chip Select/Wait Control TMP96C141AF has a built-in chip select/wait controller used to control chip select (CS0 - CS2 pins), wait (WAIT pin), and data bus size (8 or 16 bits) for any of the three block address areas. 3.6.1 Control Registers Table 3.6 (1) shows control registers One block address areas are controlled by 1-byte CS/ WAIT control registers (B0CS, B1CS, and B2CS). Registers can be written to only when the CPU is in system mode. (There are two CPU modes: system and normal.) The reason is that the settings of these registers have an important effect on the system. (1) Enable Control register bit 7 (B0E, B1E, and B2E) is a master bit used to specify enable (1)/disable (0) of the setting. Resetting B0E and B1E to disable (0) and B2E to enable (1). (2) System only specification Control register bit 6 (B0SYS, B1SYS, and B2SYS) is used to specify enable/disable of the setting depending on the CPU operating mode (system or normal). Setting this bit to 0 enables setting (Address space for CS, Wait state, Bus size, etc.) regardless of the CPU operating mode; setting it to 1 enables setting in system mode but disables setting in normal mode. Resetting clears bit 6 to 0. Bit 6 is mainly used when external memory data should not be accessed in normal mode (i.e., for system mode only memory data for the operating system). (3) CS/CAS Waveform select Control register bit 5 (B0CAS, B1CAS, and B2CAS) is used to specify waveform mode output from the chip select pin (CS0/CAS0 - CS2/CAS2). Setting this bit to 0 specifies CS0 to CS2 waveforms; setting it to 1 specifies CAS0 to CAS2 waveforms. Resetting clears bit 5 to 0. (4) Data bus size select Bit 4 (B0BUS, B1BUS, and B2BUS) of the control reg(6) ister is used to specify data bus size. Setting this bit to 0 accesses the memory in 16-bit data bus mode; setting it to 1 accesses the memory in 8-bit data bus mode. Changing data bus size depending on the access address is called dynamic bus sizing. Table 3.6 (2) shows the details of the bus operation. (5) Wait control Control register bits 3 and 2 (B0W1, 0; B1W1, 0; B2W1, 0) are used to specify the number of waits. Setting these bits to 00 inserts a 2-state wait regardless of the WAIT pin status. Setting them to 01 inserts a 1-state wait regardless of the WAIT status. Setting them to 10 inserts a 1-state wait and samples the WAIT pin status. If the pin is low, inserting the wait maintains the bus cycle until the pin goes high. Setting them to 11 completes the bus cycle without a wait regardless of the WAIT pin status. Resetting sets these bits to 00 (2-state wait mode). Address area specification Control register bits 1 and 0 (B0C1, 0; B1C1, 0; B2C1, 0) are used to specify the target address area. Setting these bits to 00 enables settings (CS output, Wait state, Bus size, etc.) as follows: * CS0 setting enabled when 7F00H to 7FFFH is accessed. * CS1 setting enabled when 480H to 7FFFH is accessed. * CS2 setting enabled when 8000H to 3FFFFFFH is accessed, for the TMP96C141, which does not have a built-in ROM. CS2 setting enabled when 10000H to 3FFFFFH is accessed for the TMP96CM40/TMP96PM40, which has built-in ROM/PROM Setting bits to 01 enables setting for all CS's blocks and outputs a low strobe signal (CS0/CAS0 ~ CS2/ CAS2) from chip select pins when 400000H to 7FFFFFH is accessed. Setting bits to 10 enables them 800000H to BFFFFFH is accessed. Setting bits to 11 enables them when C00000H to FFFFFFH is accessed. 48 TOSHIBA CORPORATION TMP96C141AF Table 3.6 (1) Chip Select/Wait Control Register Code Name Address 7 B0E Block0 CS/WAIT control register W 0068H 0 1 : CS/CAS Enable 6 B0SYS W 0 1 : SYSTEM only 5 B0CAS W 0 0 : CSO 1 : CAS0 4 B0BUS W 0 0 : 16-bit Bus 1 : 8-bit Bus B1BUS W 0 0 : 16-bit Bus 1 : 8-bit Bus B2BUS W 0 0 : 16-bit Bus 1 : 8-bit Bus W 0 W 0 3 B0W1 W 0 2 B0W0 W 0 00 : 2WAIT 01 : 1WAIT 10 : 1WAIT + n 11 : 0WAIT B1W1 B1W0 W 0 00 : 2WAIT 01 : 1WAIT 10 : 1WAIT + n 11 : 0WAIT B2W1 B2W0 W 0 00 : 2WAIT 01 : 1WAIT 10 : 1WAIT +n 11 : 0WAIT 1 B0C1 W 0 0 B0C0 W 0 B0CS 00 : 7F00H ~ 7FFFH 01 : 400000H ~ 10 : 800000H ~ 11 : C00000H ~ B1C1 W 0 B1C0 W 0 B1E Block1 CS/WAIT control register W 0069H 0 1 : CS/CAS Enable B1SYS W 0 1 : SYSTEM only B1CAS W 0 0 : CS1 1 : CAS1 B1CS 00 : 480H ~ 7FFFH 01 : 400000H ~ 10 : 800000H ~ 11 : C00000H ~ B2C1 W 0 B2C0 W 0 B2E Block2 CS/WAIT control register W 006AH 1 1 : CS/CAS Enable B2SYS W 0 1 : SYSTEM only B2CAS W 0 0 : CS2 1 : CAS2 B2CS 00 : 8000H ~ 01 : 400000H ~ 10 : 800000H ~ 11 : C00000H ~ Note: With only block 2, enable (16-bit data bus, 2-wait mode) after reset. TOSHIBA CORPORATION 49 TMP96C141AF Table 3.6 (2) Dynamic Bus Sizing Operand Data Size Operand Start Address 2n + 0 (even number) 2n + 1 (odd number) 2n + 0 (even number) 16 bits 2n + 1 (odd number) Memory Data Size 8 bits 16 bits 8 bits 16 bits 8 bits 16 bits 8 bits 16 bits CPU Data CPU Address D15 - D8 2n + 0 2n + 0 2n + 1 2n + 1 2n + 0 2n + 1 2n + 0 2n + 1 2n + 2 2n + 1 2n + 2 2n + 0 2n + 1 2n + 2 2n + 3 2n + 0 2n + 2 2n + 1 2n + 2 2n + 3 2n + 4 2n + 1 2n + 2 2n + 4 xxxxx xxxxx xxxxx b7 - b0 xxxxx xxxxx b15 - b8 xxxxx xxxxx b7 - b0 xxxxx xxxxx xxxxx xxxxx xxxxx b15 - b8 b31 - b24 xxxxx xxxxx xxxxx xxxxx b7 - b0 b23 - b16 xxxxx D7 - D0 b7 - b0 b7 - b0 b7 - b0 xxxxx b7 - b0 b15 - b8 b7 - b0 b7 - b0 b15 - b8 xxxxx b15 - b8 b7 - b0 b15 - b8 b23 - b16 b31 - b24 b7 - b0 b23 - b16 b7 - b0 b15 - b8 b23 - b16 b31 - b24 xxxxx b15 - b8 b31 - b24 8 bits 2n + 0 (even number) 32 bits 8 bits 16 bits 2n + 1 (odd number) 8 bits 16 bits xxxxx: During a read, data input to the bus is ignored. At write, the bus is at high impedance and the write strobe signal remains non-active. 50 TOSHIBA CORPORATION TMP96C141AF 3.6.2 Chip Select Image An image of the actual chip select is shown below. Out of the whole memory area, address areas that can be specified are divided into four parts. Addresses from 000000H to 3FFFFFH are divided differently: 7F00H to 7FFFH is specified for CS0; 480H to 7FFFH, for CS1; and 8000H to 3FFFFFH, for CS2. The reason is that a device other than ROM (i.e., RAM or I/O) might be connected externally. The addresses 7F00 to 7FFFH (256 bytes) for CS0 are mapped mainly for possible expansions to external I/O. The addresses 480H to 7FFFH (approximately 31K bytes) for CS1 are mapped there mainly for possible extensions to external RAM. The addresses 8000H to 3FFFFFFH (approximately 4Mbytes) for CS2 are mapped mainly for possible extensions to external ROM. After reset, CS2 is enabled in 16-bit bus and 2-wait. With the TMP96C141AF, which does not have a builtin ROM, the program is externally read at address 8000H in this setting (16-bit bus, 2-wait). With the TMP96CM40F/ TMP96PM40F, which has a built-in ROM, addresses from 8000H to FFFFFH are used as the internal ROM area; CS2 is disabled in this area. After reset, the CPU reads the program from the built-in ROM in 16-bit bus, 0-wait mode. CS0 000000H 7F00H 8000H 400000H 800000H C00000H FFFFFFH B0C1, 0 = "01" B0C1, 0 = "10" B0C1, 0 = "11" (Mainly for I/O) B0C1, 0 = "00" CS1 B1C1, 0 = "00" CS2 B2C1, 0 = "00" B1C1, 0 = "01" B1C1, 0 = "10" B1C1, 0 = "11" (Mainly for RAM) B2C1, 0 = "01" B2C1, 0 = "10" B2C1, 0 = "11" (Mainly for ROM) Supplement 1: Supplement 2: Access priority is highest for built-in I/O, then built-in memory, and lowest for the chip select/wait controller. External areas other than CS0 to CS2 are accessed in 16-bit data bus (0 wait) mode. When using the chip select/wait controller, do not specify the same address area more than once. (However, when addresses 7F00H - 7FFFH for CS0 and 480H - 7FFFH for CS1 are specified, in other words, specifications overlap, only the CS0 setting/pin is active.) TOSHIBA CORPORATION 51 TMP96C141AF 3.6.3 Example of Usage Figure 3.6 (1) is an example in which an external memory is connected to the TMP96C141AF. In this example, a ROM is connected using 16-bit Bus; a RAM is connected using 8-bit Bus. Figure 3.6 (1). Example of External Memory Connection (ROM = 16 bits, RAM and I/O = 8 bits) Resetting sets pins CS0 to CS2 to input port mode. CS0 and CS1 are set high due to an internal pull-up resistor; CS2, low due to an internal pull-down resistor. The program used to set these pins is as follows: P4CR P4FC B0CS B1CS B2CS LD LD LD LD LD EQU EQU EQU EQU EQU 0EH 10H 68H 69H 6AH ; CS0 = 8 bits, 2WAIT, 7F00H ~ 7FFFH ; CS1 = 8 bits, 0WAIT, 480H ~ 7EFFH ; CS2 = 16 bits, 1WAIT, 8000H ~ 3FFFFFH (BOCS), 90H (B1CS), 9CH (B2CS), 84H (P4CR), 07H (P4FC), 07H ) CSO, CS1, CS2 output mode setting 52 TOSHIBA CORPORATION TMP96C141AF 3.6.4 How to Start with an 8-Bit Data Bus Resetting sets the CS2 pin low due to an internal pull-down resistor; memory access starts in 16-bit data bus (2-wait) mode. To start in 8-bit data bus mode, a special operation is required. Operation is as described in the example below: B2CS EQU ORG LDX 6AH 8000H (B2CS), 9CH ; CS2 register address ; RESET address ; CS2 8-bit, 0WAIT, 8000H ~ After reset, the program reads the LDX (B2CS), 9CH instruction in 16-bit data bus mode. LDX is a 6-byte instruction: the 2nd, 4th and 6th bytes are handled as dummies (i.e., only codes in the 1st, 3rd and 5th bytes are actually used). Even if starting in 8-bit data bus mode, it is possible to program so that the LDX instruction is executed and the block 2 area (8000H - 3FFFFFH) is accessed in 8-bit data bus mode without any problem. The above program does not include setting the P42/ CS2 pin to output; add a program to set the P4CR and P4FC registers as required. TOSHIBA CORPORATION 53 TMP96C141AF 3.7 8-bit Timers The TMP96C141AF contains two 8-bit timers (timers 0 and 1), each of which can be operated independently. The cascade connection allows these timers to be used as 16-bit timer. The following four operating modes are provided for the 8-bit timers. * 8-bit interval timer mode (2 timers) * 16-bit interval timer mode (1 timer) * 8-bit programmable square wave pulse generation (PPG : variable duty with variable cycle) output mode (1 timer) * 8-bit pulse width modulation (PWM: variable duty with constant cycle) output mode (1 timer) Figure 3.7 (1) shows the block diagram of 8-bit timer (timer 0 and timer 1). Each interval timer consists of an 8-bit up-counter, 8-bit comparator, and 8-bit timer register. Besides, one timer flipflop (TFF1) is provided for pair of timer 0 and timer 1. Among the input clock sources for the interval timers, the internal clocks of T1, T4, T16, and T256 are obtained from the 9-bit prescaler shown in Figure 3.7 (2). The operation modes and timer flip-flops of the 8-bit timer are controlled by three control registers TMOD, TFFCR, and TRUN. 54 TOSHIBA CORPORATION TMP96C141AF Figure 3.7 (1). Block Diagram of 8-Bit Timers (Timers 0 and 1) TOSHIBA CORPORATION 55 TMP96C141AF Prescaler This 9-bit prescaler generates the clock input to the 8bit timers, 16-bit timer/event counters, and baud rate generators by further dividing the fundamental clock (fc) after it has been divided by 4 (fc/4). Among them, 8-bit timer uses four types of clock: T1, T4, T16, and T256. This prescaler can be run or stopped by the timer operation control register TRUN Figure 3.7 (2). Prescaler Up-counter This is an 8-bit binary counter which counts up by the input clock pulse specified by TMOD. The input clock of timer 0 is selected from the external clock from T10 pin and the three internal clocks T1 (8/fc), T4 (32/fc), and T16 (128/fc), according to the set value of TMOD register. The input clock of timer 1 differs depending on the operation mode. When set to 16-bit timer mode, the overflow output of timer 0 is used as the input clock. When set to any other mode than 16-bit timer mode, the input clock is selected from the internal clocks T1 (8/fc), T16 (128/fc), and T256 (2048/fc) as well as the comparator output (match detection signal) of timer 0 according to the set value of TMOD register. 56 Example : When TMOD TOSHIBA CORPORATION TMP96C141AF Timer register This is an 8-bit register for setting an interval time. When the set value of timer registers TREG0, TREG1, matches the value of up-counter, the comparator match detect signal becomes active. If the set value is 00H, this signal becomes active when the up-counter overflows. Timer register TREG0 is of double buffer structure, each of which makes a pair with register buffer. The timer flip-flop control register TFFCR Figure 3.7 (3). Configuration of Timer Register 0 Note : Timer register and the register buffer are allocated to the same memory address. When The memory address of each timer register is as follows. TREG0: 000022H TREG1: 000023H All registers are write-only and cannot be read. Comparator A comparator compares the value in the up-counter with the values to which the timer register is set. When they match, the up-counter is cleared to zero and an interrupt signal (INTT0, INTT1) is generated. If the timer TOSHIBA CORPORATION flip-flop inversion is enabled, the timer flip-flop is inverted at the same time. | Timer flip-flop (timer F/F: TFF1) The status of the timer flip-flop is inverted by the match detect signal (comparator output) of each interval timer and the value can be output to the timer output pins TO1 (also used as P71). A timer F/F is provided for a pair of timer 0 and timer 1 and is called TFF1. TFF1 is output to TO1 pin. 57 TMP96C141AF Figure 3.7 (4). Timer Operation Control Register (TRUN) 58 TOSHIBA CORPORATION TMP96C141AF Figure 3.7 (5). Timer Mode Control Register (TMOD) TOSHIBA CORPORATION 59 TMP96C141AF Figure 3.7 (6). Timer Flip-Flop Control Register (TFFCR) 60 TOSHIBA CORPORATION TMP96C141AF The operation of 8-bit timers will be described below: (1) 8-bit timer mode Two interval timers 0, 1, can be used independently as 8-bit interval timer. All interval timers operate in the same manner, and thus only the operation of timer 1 will be explained below. Generating interrupts in a fixed cycle To generate timer 1 interrupt at constant intervals using timer 1 (INTT1), first stop timer 1 then set the operation mode, input clock, and a cycle to TMOD and TREG1 register, respectively. Then, enable interrupt INTT1 and start the counting of timer 1. Example: To generate timer 1 interrupt every 40 microseconds at fc = 16 MHz, set each register in the following manner. MSB 7 TRUN TMOD TREG1 INTET10 TRUN Note: LSB 6 x 0 1 1 x 5 - x 0 0 - 4 - x 1 1 - 3 - 0 0 - - 2 - 1 0 - - 1 0 - 0 - 1 0 - - 0 - - Stop timer 1, and clear it to "0". Set the 8-bit timer mode, and select T1 (0.5s @ fc = 16MHz) as the input clock. Set the timer register at 40s T1 = 50H. Enable INTT1, and set it to "Level 5". Start timer 1 counting. - 0 0 1 1 x; don't care -; no change Use the following table for selecting the input clock. Table 3.7 (1) 8-Bit Timer Interrupt Cycle and Input Clock Input Clock Interrupt Cycle (at fc = 16MHz) 0.5s ~ 128s 2s ~ 512s 8s ~ 2.048ms 128s ~ 32.708ms Resolution 0.5s 2s 8s 128s Interrupt Cycle (at fc = 20MHz) 0.4s ~ 102.4s 1.6s ~ 409.6s 6.4s ~ 1.638ms 102.4s ~ 2.621ms Resolution 0.4s 1.6s 6.4s 128s T1 (8/fc) T4 (32/fc) T16 (128/fc) T256 (2048/fc) Note: The input clock of timer 0 and timer 1 are different from as follows: Timer 0: T10 input, T1, T4, T16 Timer 1: Match Output of Timer 0, T1, T16, T256 TOSHIBA CORPORATION 61 TMP96C141AF Generating a 50% duty square wave pulse The timer flip-flop (TFF1) is inverted at constant intervals, and its status is output to timer output pin (TO1). Example: To output a 3.0s square wave pulse from TO1 pin at fc = 16MHz, set each register in the following procedures. Either timer 0 or timer 1 may be used, but this example uses timer 1. 7 TRUN TMOD TREG1 TFFCR P7CR P7FC TRUN Note: 6 x 0 0 - x x x 5 - x 0 - x x - 4 - x 0 - x x - 3 - 0 0 1 - - - 2 - 1 0 0 - - - 1 0 - 1 1 1 1 1 0 - - 1 1 - x - Stop timer 1, and clear it to "0". Set the 8-bit timer mode, and select T1 (0.5s @ fc = 16MHz) as the input clock. Set the timer register at 3.0s / T1 / 2 = 3. Clear TFF1 to "0", and set to invert by the match detect signal from timer 1. - 0 0 - x x 1 ) Select P71 as TO1 pin. Start timer 1 counting. x; don't care -; no change Figure 3.7 (7). Square Wave (50% Duty) Output Timing Chart 62 TOSHIBA CORPORATION TMP96C141AF Making timer 1 count up by match signal from timer 0 comparator Set the 8-bit timer mode, and set the comparator output of timer 0 as the input clock to timer 1. Figure 3.7 (8). Timer 1 Count Up by Timer 0 Output inversion with software The value of timer flip-flop (TFF1) can be inverted, independent of timer operation. Writing "00" into TFFCR Note: The value of timer register cannot be read. 16-bit timer mode A 16-bit interval timer is configured by using the pair of timer 0 and timer 1. To make a 16-bit interval timer by cascade connecting timer 0 and timer 1, set timer 0/timer 1 mode register TMOD Table 3.7 (2) 16-Bit Timer (Interrupt) and Input Clock Input Clock Interrupt Cycle (at fc = 16MHz) 0.5s ~ 32.786ms 2s ~ 131.072ms 8s ~ 524.288ms Resolution 0.5s 2s 8s Interrupt Cycle (at fc = 20MHz) 0.4s ~ 26.214ms 1.6s ~ 104.857ms 6.4s ~ 419.430ms Resolution 0.4s 1.6s 6.4s T1 (8/fc) T4 (32/fc) T16 (128/fc) TOSHIBA CORPORATION 63 TMP96C141AF The lower 8 bits of the timer (interrupt) cycle are set by the timer register TREG0, and the upper 8 bits are set by TREG1. Note that TREG0 always must be set first. (Writing data into TREG0 disables the comparator temporarily, and the comparator is restarted by writing data into TREG1.) Setting example: To generate an interrupt INTT1 every 0.5 seconds at fc = 16MHz, set the following values for timer registers TREG0 and TREG: When counting with input clock of T16 (8s @ 16MHz) 0.5 sec / 8s = 62500 = F424H Therefore, set TREG1 = F4H and TREG0 = 24H, respectively. The comparator match signal is output from timer 0 each time the up-counter UC0 matches TREG0, where the up-counter UC0 is not to be cleared. With the timer 1 comparator, the match detect signal is output at each comparator timing when up-counter UC1 and TREG1 values match. When the match detect signal is output simultaneously from both comparators of timer 0 and timer 1, the up-counters UC0 and UC1 are cleared to "0", and the interrupt INTT1 is generated. If inversion is enabled, the value of the timer flip-flop TFF1 is inverted. Example: When TREG1 = 04H and TREG0 = 80H Figure 3.7 (9). Output Timer by 16-Bit Timer Mode (3) 8-bit PPG (Programmable Pulse Generation) Output mode Square wave pulse can be generated at any frequency and duty by timer 0 and timer 1. The output pulse may be either low-active or high-active. In this mode, timer 1 cannot be used. Timer 0 outputs pulse to TO1 pin (also used as P70). In this mode, a programmable square wave is generated by inverting timer output each time the 8-bit up- counter (UC0) matches the timer registers TREG0 and TREG1. However, it is required that the set value of TREG0 is smaller than that of TREG1. Though the up-counter (UC1) of timer 1 is not used in this mode, UC1 should be set for counting by setting TRUN 64 TOSHIBA CORPORATION TMP96C141AF Figure 3.7 (10). 8-Bit PPG Output Waveforms Figure 3.7 (11). Block Diagram of 8-Bit PPG Output Mode TOSHIBA CORPORATION 65 TMP96C141AF When the double buffer of TREG0 is enabled in this mode, the value of register buffer will be shifted in TREG0 each time TREG1 matches UC0. Use of the double buffer makes easy handling of low duty waves (when duty is varied). Figure 3.7 (12). Operation of Register Buffer Example: Generating 1/4 duty 50KHz pulse @ fc = 16MHz) * Calculate the value to be set for timer register. To obtain the frequency 50KHz, the pulse cycle t should be: t = 1/50KHz = 20s. Given T1 = 0.5s @ 16MHz), 20s / 0.5s = 40 Consequently, to set the timer register 1 (TREG1) to TREG1 = 40 = 28H and then duty to 1/4, t x 1/4 = 20s x 1/4 = 5s 5s / 0.5s = 10 Therefore, set timer register 0 (TREG0) to TREG0 = 10 = 0AH. 7 TRUN TMOD TREG0 TREG1 TFFCR P7CR P7FC TRUN - 1 0 0 - x x 1 6 x 0 0 0 - x x x 5 - x 0 1 - x x - 4 - x 0 0 1 x x - 3 - x 1 1 0 - - - 2 - x 0 0 1 - - - 1 0 0 1 0 1 1 1 1 0 0 1 0 0 x - x 1 Stop timer 0, and clear it to "0". Set the 8-bit PPG mode, and select T1 as input clock. Write "0AH". Write "28H". Sets TFF1 and enables the inversion and double buffer enable. Writing "10" provides negative logic pulse. ) Set P71 as TO1 pin. Start timer 0 and timer 1 counting. Note : x; don't care -; no change 66 TOSHIBA CORPORATION TMP96C141AF (4) 8-bit PWM Output mode This mode is valid only for timer 0. In this mode, maximum 8-bit resolution of PWM pulse can be output. PWM pulse is output to TO1 pin (also used as P71) when using timer 0. Timer 1 can also be used as 8-bit timer. Timer output is inverted when up-counter (UC0) matches the set value of timer register TREG0 or when 2n - 1 (n = 6, 7, or 8; specified by T01MOD Figure 3.7 (13). 8-Bit PWM Waveforms TOSHIBA CORPORATION 67 TMP96C141AF Figure 3.7 (14) shows the block diagram of this mode. Figure 3.7 (14). Block Diagram of 8-Bit PWM Mode In this mode, the value of register buffer will be shifted in TREG0 if 2n - 1 overflow is detected when the double buffer of TREG0 is enabled. Use of the double buffer makes the handling of small duty waves easy. Figure 3.7 (15). Operation of Register Buffer Example: To output the following PWM waves to TO1 pin at fc = 16MHz. To realize 63.5s of PWM cycle by T1 = 0.5s (@ fc = 16MHz), 63.5s / 0.5s = 127 = 27 - 1 Consequently, n should be set to 7. As the period of low level is 36s, for T1 = 0.5s, set the following value for TREG0: 36s / 0.5s = 72 = 48H 68 TOSHIBA CORPORATION TMP96C141AF MSB 7 TRUN TMOD TREG0 TFFCR P7CR P7FC TRUN Note: LSB 6 x 1 1 x x x x 5 - 1 0 x x x - 4 - 0 0 x x x - 3 - - 1 1 - - - 2 - - 0 0 - - - 1 - 0 0 1 1 1 - 0 0 1 0 x - x 1 Stop timer 0, and clear it to "0". Set 8-bit PWM mode (cycle: 27 - 1) and select T1 as the input clock. Write "48H". Clears TFF1, enables the inversion and double buffer. 1 0 x x x 1 ) Set P71 as the TO1 pin. Start timer 0 counting. x; don't care -; no change Table 3.7 (3) PWM Cycle and the Setting of 2n -1 Counter PWM Cycle (@ fc =16MHz) PWM Cycle (@ fc = 20 MHz) T1 26-1 2 2 7-1 8-1 T4 126msec (7.9kHz) 254msec (3.9kHz) 510msec (1.9kHz) T16 0.50sec (1.9kHz) 1.01sec (0.98kHz) 2.04sec (0.49kHz) T1 25.2sec (39.0kHz) 50.8sec (19.7kHz) 102sec (9.80kHz) T4 100sec (10.0kHz) 203sec (4.9kHz) 408sec (2.4kHz) T16 0.40msec (2.4kHz) 0.81msec (1.2kHz) 1.63msec (0.61kHz) 31.5sec (31.7kHz) 63.5sec (15.7kHz) 127sec (7.8kHz) (5) Table 3.7 (4) shows the list of 8-bit timer modes. Table 3.7 (4) Timer Mode Setting Registers Register Name Name of Function in Function T10M Timer Mode PWMM PWM0 Cycle TMOD T1CLK Upper Timer Input Clock - Lower timer match : T1, T16, T256 (00, 01, 10, 11) - T0CLK Lower Timer Input Clock External clock, T1, T4, T16 (00, 01, 10, 11) External clock, T1, T4, T16 (00, 01, 10, 11) External clock, T1, T4, T16 (00, 01, 10, 11) External clock, T1, T4, T16 (00, 01, 10, 11) TFFCR TFF1IS Timer F/F Invert Signal Select - 16-bit timer mode 01 - 8-bit timer x 2 channels 00 - 0 : Lower timer output 1 : Upper timer output 8-bit PPG x 1 channel 10 - - 8-bit PWM x 1 channel 11 26 - 1, 27 - 1, 28 - 1 (01, 10, 11) - - 8-bit timer x 1 channel Note: -: don't care 11 - T1, T16, T256 (01, 10, 11) - Output disabled TOSHIBA CORPORATION 69 TMP96C141AF 3.8 8-Bit PWM Timer The TMP96C141AF/TMP96CM40F/TMP96PM40F has two built-in 8-bit PWM timers (timers 2 and 3). They have two operating modes. * 8-bit PWM (pulse width modulation: variable duty at fixed interval) output mode * 8-bit interval timer mode Figure 3.8 (1) is a block diagram of 8-bit PWM timer (timers 2 and 3). PWM timers consist of an 8-bit up-counter, 8-bit comparator, and 8-bit timer register. Two timer flip-flops (TFF2 for timer 2 and TFF3 for timer 3) are provided. Input clocks P1, P4, and P16 for the PWM timers can be obtained using the built-in prescaler. PWM timer operating mode and timer flip-flops are controlled by four control registers (P0MOD, P1MOD, PFFCR, and TRUN). 70 TOSHIBA CORPORATION TMP96C141AF Figure 3.8 (1). Block Diagram of 8-Bit PWM Timer 0 (Timer 2) Note: Block diagram for 8-bit PWM timer 1 (timer 3) is the same as the above diagram. TOSHIBA CORPORATION 71 TMP96C141AF Prescaler Generates input clocks dedicated to PWM timers by further dividing the fundamental clock (fc) after it has been divided by 2 (fc/2). Since the register used to control the prescaler is the same as the one for other timers, the prescaler cannot be operated independently. The PWM timer uses three input clocks: /P1, /P4, and /P16. Like the 9-bit prescaler described in the 8-bit timer section, this prescaler can be counted/stopped using bit 7 Dedicated Prescaler Cycle 16MHz 20MHz 200ns 800ns 3.2sc P1 (4/fc) 250ns 1s 4s P4 (16/fc) P16 (64/fc) Figure 3.8 (2). Prescaler Up-counter An 8-bit binary counter which counts up using the input clock specified by PWM mode register (P0MOD or P1MOD). The input clock for the PWM0/PWM1 is selected from the internal clocks P1, P4, and P16 (PWM dedicated prescaler output) depending on the value set in the P0MOD/P1MOD register. Operating mode is also set by P0MOD and P1MOD registers. At reset, they are initialized to P0MOD 72 match. Count/stop and clear of the up-counter can be controlled for each PWM timer using the timer operation control register TRUN. Resetting clears all up-counters and stops timers. Timer registers Two 8-bit registers used for setting an interval time. When the value set in the timer registers (TREG 2 and 3) matches the value in the up-counter, the match detect signal of the comparator becomes active. Timer registers TREG2 and TREG3 are each paired with register buffer to make a double buffer structure. TOSHIBA CORPORATION TMP96C141AF TREG2 and TREG3 are controlled double buffer enable/disable by P0MOD Figure 3.8 (3). Structure of Timer Registers 2 and 3 Note: The timer register and register buffer are allocated to the same memory address. When Memory addresses of the timer registers are as follows: TREG2 : 000026H TREG3 : 000027H the comparator outputs the match detect signal. A timer interrupt (INTT2/INTT3) is generated at compare and match if the interrupt select bit Both timer registers are write only; however, register buffer values can be read when reading the above addresses. Comparator Compares the value in the up-counter with the value in the timer register (TREG2/TREG3). When they match, TOSHIBA CORPORATION 73 TMP96C141AF Figure 3.8 (4). 8-Bit PWM0 Mode Control Register 74 TOSHIBA CORPORATION TMP96C141AF Figure 3.8 (5). 8-Bit PWM1 Mode Control Register TOSHIBA CORPORATION 75 TMP96C141AF Figure 3.8 (6). 8-Bit PWM F/F Control Register 76 TOSHIBA CORPORATION TMP96C141AF Figure 3.8 (7). Timer Operation Control Register (TRUN) TOSHIBA CORPORATION 77 TMP96C141AF The following explains PWM timer operations. (1) PWM timer mode Both PWM timers can output 8-bit resolution PWM independently. Since both timers operate in exactly the same way, PWM0 is used for purposes of explanation. PWM output changes under the following two conditions. Condition 1: * TFF2 is cleared to 0 when the value in the upcounter (UC2) and the value set in the TREG2 match. * TFF2 is set to 1 when a 2n - 1 counter overflow (n = 6, 7, or 8) occurs. Condition 2: * TFF2 is set to 1 when the value in the up-counter (UC2) and the value set in TREG2 match. * TFF2 is cleared to 0 when a 2n - 1 counter over flow (n = 6, 7, or 8) occurs. The up-counter (UC2) is cleared by a 2n - 1 counter overflow. The PWM timer can output 0% - 100% duty pulses because a 2n - 1 counter overflow has a higher priority. That is, to obtain 0% output (always low), the mode used to set TFF2 to 0 due to overflow (PFFCR PWM timing Figure 3.8 (8). Output Waves in PWM Timer Mode Note: The above waves are obtained in a mode where the F/F is set by a match with the timer register (TREG) and reset by an overflow. 78 TOSHIBA CORPORATION TMP96C141AF Figure 3.8 (9) is a block diagram of this mode. Figure 3.8 (9). Block Diagram of PWM Timer Mode (PWM0) In this mode, enabling double buffer is very useful. The register buffer value shifts into TREG2 when a 2n -1 overflow is detected, when double buffer is enabled. Using double buffer makes handling small duty waves easy. Figure 3.8 (10). Register Buffer Operation TOSHIBA CORPORATION 79 TMP96C141AF Example: To output the following PWM waves to TO2 pin using PWM0 at fc = 16MHz. To implement 31.75s PWM cycle by P1 = 0.25s (@ fc = 16MHz) 31.75s / 0.25s = 127 = 27 -1. Consequently, set n to 7. Since the low level cycle = 15s; for P1 = 0.25s 15s / 0.25 = 60 = 3CH set the 3CH in TREG2. 7 TRUN P0MOD TREG2 P0MOD PFFCR P7CR P7FC TRUN Note: 6 x 0 0 1 - x x x 5 - 0 1 0 - x x - 4 - 0 1 0 - x x - 3 - 0 1 0 0 - - - 2 0 0 1 0 1 1 1 1 1 - 0 0 0 1 - - - 0 - 1 0 1 1 - x - Stops PWM0 and clears it to 0. Sets PWM (27 - 1) mode, input clock P1, overflow interrupt, and disables double buffer. Writes 3CH. Enables double buffer. Sets TFF2 and a mode where TFF2 is set by compare and match, and cleared by overflow. - 0 - - x x 1 ) Sets P72 as the TO2 pin. Starts PWM0 counting. x; don't care -; no change Table 3.8 (1) PWM Cycle and 2n -1 Counter Setting 16MHz Formula 26-1 27-1 28-1 26-1 - Pn 27-1 - Pn 28-1 - Pn 20MHz P1 15.8sec (63kHz) 31.8sec (31kHz) 63.8sec (16kHz) P4 63.0sec (16kHz) 127.0sec (7.9kHz) 255.0sec (3.9kHz) P16 252sec (3.9kHz) 508sec (1.9kHz) 1020sec (0.98kHz) P1 12.6sec (79kHz) 25.4sec (39kHz) 51.0sec (20kHz) P4 50.4sec (20kHz) 101.6sec (9.8kHz) 204.0sec (4.9kHz) P16 201sec (4.9kHz) 406sec (2.5kHz) 816sec (1.2kHz) 80 TOSHIBA CORPORATION TMP96C141AF (2) 8-bit timer mode Both PWM timers can be used independently as 8-bit interval timers. Since both timers operate in exactly the same way, PWM0 (timer 2) is used for the purposes of explanation. Generating interrupts at a fixed interval To generate timer 2 interrupt (INTT2) at a fixed interval using PWM0 timer, first stop PWM0, then set the operating mode, input clock, and interval in the P0MOD and TREG2 registers. Next, enable INTT2 and start counting PWM0. Example: To generate a timer 2 interrupt every 40s at fc = 16MHz, set registers as follows: 7 TRUN P0MOD TREG2 TRUN Note: 6 x 0 0 - x 5 - 1 1 - - 4 - 1 0 - - 3 - 0 0 1 - 2 0 0 0 1 1 1 - x 0 0 - 0 - x 0 0 - Stops PWM0 and clears it to 0. Sets 8-bit timer mode and selects P1 (0.25s) and compare interrupt. Sets 40s/0.25s = A0H in timer register. Enables INTT2 and sets interrupt level 4. Starts PWM0 counting. - x 1 - 1 INTEPW10 x; don't care -; no change Select an input clock using the table below. Table 3.8 (2) Interrupt Cycle and Input Clock Selection using 8-Bit Timer Mode Input Clock Interrupt Cycle (at fc = 16MHz) 0.25s ~ 64s 1s ~ 256s 4s ~ 1024s Resolution 0.25s 1s 4s Interrupt Cycle (at fc = 20MHz) 0.2s ~ 51.2s 0.8s ~ 204.8s 3.2s ~ 819.2s Resolution 0.2s 0.8s 3.2s P1 (4/fc) P4 (16/fc) P16 (64/fc) Note: To generate interrupts in 8-bit timer mode, bit 5 (interrupt control bit TOSHIBA CORPORATION 81 TMP96C141AF Generating a 50% square wave To generate a 50% square wave, invert the timer flipflop at a fixed interval and output the timer flip-flop value to the timer output pin (TO2). Example: To output a 3.0s square wave at fc = 16MHz from TO2 pin, set register as fol- lows: 7 TRUN P0MOD TREG2 PFFCR P7CR P7FC TRUN Note: 6 x 0 0 - x x x 5 - 1 0 - x x - 4 - 1 0 - x x - 3 - 0 0 1 - - - 2 0 0 1 0 1 1 1 1 - x 1 0 - - - 0 - x 0 1 - x - Stops PWM0 and clears it to 0. Sets 8-bit timer mode and selects P1 (0.25s) as the input clock. Sets 3.0s/0.25s/2 = 6 in the timer register. - x 0 - x x 1 ) Sets P72 as the TO2 pin. Clears TFF2 to 0 and inverts using comparator output. x; don't care -; no change Figure 3.8 (11). Square Wave (50% Duty) Output Timing Chart 82 TOSHIBA CORPORATION TMP96C141AF This mode is as shown in Figure 3.8 (12) below. Figure 3.8 (12). Block Diagram of 8-Bit Timer Mode TOSHIBA CORPORATION 83 TMP96C141AF 3.9 16-Bit Timer The TMP96C141AF has two (timer 4 and timer 5) multifunctional 16-bit timer/event counter with the following operation modes. * 16-bit interval timer mode * 16-bit event counter mode * 16-bit programmable pulse generation (PPG) mode * Frequency measurement mode * Pulse width measurement mode * Time differential measurement mode Timer/event counter consists of 16-bit up-counter, two 16-bit timer registers, two 16-bit capture registers (one of them applies double-buffer), two comparators, capture input controller, and timer flip-flop and the control circuit. Timer/event counter is controlled by four control registers: T4MOD/T5MOD, T4FFCR/T5FFCR, TRUN and T45CR. Figure 3.9 (1) and (2) show the block diagram of 16-bit timer/event counter (timer 4 and timer 5). 84 TOSHIBA CORPORATION TMP96C141AF Figure 3.9 (1). Block Diagram of 16-Bit Timer (Timer 4) TOSHIBA CORPORATION 85 TMP96C141AF Figure 3.9 (2). Block Diagram of 16-Bit Timer (Timer 5) 86 TOSHIBA CORPORATION TMP96C141AF Figure 3.9 (3). 16-Bit Timer Mode Controller Register (T4MOD) (1/2) TOSHIBA CORPORATION 87 TMP96C141AF Figure 3.9 (4). 16-Bit Controller Register (T4MOD) (2/2) 88 TOSHIBA CORPORATION TMP96C141AF Figure 3.9 (5). 16-Bit Timer 4 F/F Control (T4FFCR) TOSHIBA CORPORATION 89 TMP96C141AF Figure 3.9 (6). 16-Bit Timer Mode Control Register (T5MOD) (1/2) 90 TOSHIBA CORPORATION TMP96C141AF Figure 3.9 (7). 16-Bit Timer Control Register (T5MOD) (2/2) TOSHIBA CORPORATION 91 TMP96C141AF CAP4T6 CAP3T6 EQ7T6 EQ6T6 : Invert when the up-counter value is loaded to CAP4 : Invert when the up-counter value is loaded to CAP3 : Invert when up-counter matches TREG7 : Invert when up-counter matches TREG6 Figure 3.9 (8). 16-Bit Timer 5 F/F Control (T5FFCR) 92 TOSHIBA CORPORATION TMP96C141AF DB6EN DB4EN : Double buffer of TREG6 : Double buffer of TREG4 Figure 3.9 (9). 16-Bit Timer (Timer 4, 5) Control Register (T45CR) Figure 3.9 (10). Timer Operation Control Register (TRUN) TOSHIBA CORPORATION 93 TMP96C141AF Up-counter (UC4/UC5) UC4/UC5 is a 16-bit binary counter which counts up according to the input clock specified by T4MOD TREG4 Upper 8 bits 000031H TREG6 Upper 8 bits 000041H Lower 8 bits 000040H Upper 8 bits 000043H Lower 8 bits 000030H Upper 8 bits 000033H TREG7 Lower 8 bits 000042H timer register TREG5, TREG7. The "clear enable/disable" is set by T4MOD TREG5 Lower 8 bits 000032H TREG4 and TREG6 timer register is of double buffer structure, which is paired with register buffer. The timer control register T45CR CAP 1 Upper 8 bits 000035H CAP 3 Upper 8 bits 000045H Lower 8 bits 000044H Lower 8 bits 000034H the same memory addresses 000030H/000031H/ 0000400H/000041H. When CAP 2 Upper 8 bits 000037H CAP 4 Upper 8 bits 000047H Lower 8 bits 000046H Lower 8 bits 000036H Capture Input Control This circuit controls the timing to latch the value of up-counter UC4/UC5 into (CAP1, CAP2)/(CAP3, CAP4). 94 The latch timing of capture register is controlled by register T4MOD TOSHIBA CORPORATION TMP96C141AF * When T4MOD Note: This flip-flop (TFF5) is contained only in the 16-bit timer 4. (1) 16-bit Timer Mode Timer 4 and 5 operate independently. Since both timers operate in exactly the same way, timer 4 is used for the purposes of explanation. Generating interrupts at fixed intervals: In this example, the interval time is set in the timer register TREG5 to generate the interrupt INTTR5. 7 TRUN - 1 1 0 * * TRUN Note: 6 x 1 1 0 * * x 5 - 0 0 1 * * - 4 0 0 0 0 * * 1 3 - 1 0 0 * * - 2 - 0 0 1 * * - 1 - 0 1 * * * - 0 - 0 1 * * * - Start timer 4. Stop timer 4. Enable INTTR5 and sets interrupt level 4. Disables INTTR4. Disable trigger. Select internal clock for input and disable the capture function. Set the interval timer (16 bits). INTET54 T4FFCR T4MOD TREG5 (** = 01, 10, 11) 1 x; don't care -; no change (2) 16-bit Event Counter Mode In 16-bit timer mode as described in above, the timer can be used as an event counter by selecting the external clock (TI4/ TI6 pin input) as the input clock. To read the value of the TOSHIBA CORPORATION counter, first perform "software capture" once and read the captured value. The counter counts at the rise edge of TI4/TI6 pin input. TI4/TI6 pin can also be used as P80/INT4 and P84/INT6. Since both timers operate in exactly the same way, timer 4 is used for the purposes of explanation. 95 TMP96C141AF 7 TRUN P8CR - - 1 1 0 * 1 6 x - 1 1 0 * x 5 - - 0 0 1 * - 4 0 - 0 0 0 * 1 3 - - 1 0 0 * - 2 - - 0 0 1 * - 1 - - 0 1 0 * - 0 - 0 0 1 0 * - Stop timer 4. Set P80 to input mode. Enable INTTR5 and sets interrupt level 4, while disables INTTR4. T4FFCR T4MOD TREG5 TRUN Note: INTET54 Disable trigger. Select TI4 as the input clock. Set the number of counts (16 bits). Start timer 4. When used as an event counter, set the prescaler in RUN mode. (3) 16-bit Programmable Pulse Generation (PPG) Output Mode Since both timers operate in exactly the same way, timer 4 is used for the purposes of explanation. The PPG mode is obtained by inversion of the timer flip-flop TFF4 that is to be enabled by the match of the up-counter UC4 with the timer register TREG4 or 5 and to be output to TO4 (also used as P82). In this mode, the following conditions must be satisfied. (Set value of TREG4) < (Set value of TREG5) 7 TRUN TREG4 TREG5 T45CR T4FFCR T4MOD P8CR P8FC TRUN Note: 6 x * * x 1 0 - - x 5 - * * x 0 1 - x - 4 0 * * x 0 0 - x 1 3 - * * - 1 0 - - - 2 - * * - 1 1 1 1 - 1 - * * - 0 * - x - 0 - * * 1 0 * - x - Stop timer 4. Set the duty (16 bits). Set the cycle (16 bits). Double buffer of TREG4 enable. (Changes the duty and cycle at the interrupt INTTR5) Set the mode to invert TFF4 at the match with TREG4/TREG5, and also sets TFF4 to "0". Select internal clock for input and disables the capture function. - * * 0 1 0 - x 1 (** = 01, 10, 11) ) Assign P82 as TO4. Start timer 4. x; don't care -; no change Figure 3.9 (11). Programmable Pulse Generation (PPG) Output Waveforms 96 TOSHIBA CORPORATION TMP96C141AF When the double buffer of TREG4 is enabled in this mode, the value of register buffer 4 will be shifted in TREG4 at match with TREG5. This feature makes easy the handling of low duty waves. Figure 3.9 (12). Operation of Register Buffer Shows the block diagram of this mode. Figure 3.9 (13). Block Diagram of 16-Bit PPG Mode TOSHIBA CORPORATION 97 TMP96C141AF (4) Application Examples of Capture Function The loading of up-counter (UC4) values into the capture registers CAP1 and CAP2, the timer flip-flop TFF4 inversion due to the match detection by comparators CP4 and CP5, and the output of TFF4 status to TO4 pin can be enabled or disabled. Combined with interrupt function, they can be applied in many ways, for example: One-shot pulse output from external trigger pulse Frequency measurement Pulse width measurement Time difference measurement One-Shot Pulse Output from External Trigger Pulse Set the up-counter UC4 in free-running mode with the internal input clock, input the external trigger pulse from TI4 pin, and load the value of up-counter into capture register CAP1 at the rise edge of the TI4 pin. Then set to T4MOD Figure 3.9 (14). One-Shot Pulse Output (with Delay) 98 TOSHIBA CORPORATION TMP96C141AF Setting Example: To output 2ms one-shot pulse with 3ms delay to the external trigger pulse to TI4 pin. Keep counting (Free-running). Main setting T4MOD T4FFCR - 1 - 1 1 0 0 0 1 0 0 0 0 1 1 Load the up-counter value into CAP1 at the rise edge of TI4 pin input. 0 Clear TFF4 to zero. Disable TFF4 inversion. P8CR P8FC INTE45 TRUN - x - 1 1 - - - 0 x - x - 0 - - x - 0 1 - - 1 1 - 1 1 1 0 - - x 0 0 - - x 0 0 - Start timer 4. Count with T1. ) Select P82 as the TO4 pin. Enable INT4, and disables INTTR4 and INTTR5. INTET54 Setting of INT4 TREG4 TREG5 T4FFCR - 1 CAP1 + 3ms/T1 TREG4 + 2ms/T1 - 1 - 0 - 0 1 - 1 - - - - Enable TFF4 inversion when the up-counter value matches TREG4 or 5. INTET54 Setting of INT5 T4FFCR - 1 - 0 - 0 - 0 0 - 0 - - - - Disable TFF4 inversion when the up-counter value matches TREG 4 or 5. INTET54 Note: - Enable INTTR5. - Disable INTTR5. x; don't care -; no change When delay time is unnecessary, invert timer flip-flop TFF4 when the up-counter value is loaded into capture register 1 (CAP1), and set the CAP1 value (c) plus the one-shot pulse width (p) to TREG5 when the interrupt INT4 occurs. The TFF4 inversion should be enabled when the up-counter (UC4) value matches TREG5, and disabled when generating the interrupt INTTR5. TOSHIBA CORPORATION 99 TMP96C141AF Figure 3.9 (15). One-Shot Pulse Output (without Delay) Frequency Measurement The frequency of the external clock can be measured in this mode. The clock is input through the TI4 pin, and its frequency is measured by the 8-bit timers (Timer 0 and Timer 1) and the 16-bit timer/event counter (Timer 4). The TI4 pin input should be selected for the input clock of Timer 4. The value of the up-counter is loaded into the capture register CAP1 at the rise edge of the timer flip-flop TFF1 of 8-bit timers (Timer 0 and Timer 1), and into CAP2 at its fall edge. The frequency is calculated by the difference between the loaded values in CAP1 and CAP2 when the interrupt (INTT0 or INTT1) is generated by either 8-bit timer. Figure 3.9 (16). Frequency Measurement For example, if the value for the level "1" width of TFF1 of the 8-bit timer is set to 0.5 sec. and the differ- ence between CAP1 and CAP2 is 100, the frequency will be 100/0.5 [sec.] = 200 [Hz]. 100 TOSHIBA CORPORATION TMP96C141AF Pulse Width Measurement This mode allows measuring the "H" level width of an external pulse. While keeping the 16-bit timer/event counter counting (free-running) with the internal clock input, the external pulse is input through the TI4 pin. Then the capture function is used to load the UC4 values into CAP1 and CAP2 at the rising edge and falling edge of the external trigger pulse respectively. The interrupt INT4 occurs at the falling edge of TI4. The pulse width is obtained from the difference between the values of CAP1 and CAP2 and the internal clock cycle. For example, if the internal clock is 0.8 microseconds and the difference between CAP1 and CAP2 is 100, the pulse width will be 100 x 0.8 = 80 microseconds. Figure 3.9 (17). Pulse Width Measurement Note: Only in this pulse width measuring mode (T4MOD The width of "L" level can be measured from the difference between the first C2 and the second C1 at the second INT4 interrupt. Time Difference Measurement This mode is used to measure the difference in time between the rising edges of external pulses input through TI4 and TI5. Keep the 16-bit timer/event counter (Timer 4) counting (free-running) with the internal clock, and load the UC4 value into CAP1 at the rising edge of the input pulse to TI4. Then the interrupt INT4 is generated. Similarly, the UC4 value is loaded into CAP2 at the rising edge of the input pulse to TI5, generating the interrupt INT5. The time difference between these pulses can be obtained from the difference between the time counts at which loading the up-counter value into CAP1 and CAP2 has been done. TOSHIBA CORPORATION 101 TMP96C141AF Figure 3.9 (18). Time Difference Measurement (5) Different Phased Pulses Output Mode In this output mode, signals with any different phase can be outputted by free-running up-counter UC4. When the value in up-counter UC4 and the value in TREG4 (TREG5) match, the value in TFF4 (TFF5) is inverted and output to TO4 (TO5). This mode can only be used by 16-bit timer 4. Figure 3.9 (19). Phase Output Cycles (counter overflow time) of the above output waves are listed below. T1 T4 T16 16MHz 1.024msec 4.096msec 16.38 msec 20MHz 0.819msec 3.277msec 13.11 msec 102 TOSHIBA CORPORATION TMP96C141AF 3.10 Stepping Motor Control/Pattern Generation Port The TMP96C141AF has two channels (PG0 and PG1) of 4-bit hardware stepping motor control/pattern generation (herein after called PG) which actuate in synchronization with the (8bit/16-bit) timers. The PG (PG0 and PG1) are shared in 8-bit I/ O ports P6. Channel 0 (PG0) is synchronous with 8-bit timer 0 or timer 1, 16-bit timer 5, to update the output. The PG ports are controlled by control registers (PG01CR) and can select either stepping motor control mode or pattern generation mode. Each bit of the P6 can be used as the PG port. PG0 and PG1 can be used independently. All PG operate in the same manner except the following points, and thus only the operation of PG0 will be explained below. Differences between PG0 and PG1 PG0 Trigger Signal from Timer 4 PG1 from Timer 5 Figure 3.10 (1). Port 6/PG Circuit TOSHIBA CORPORATION 103 TMP96C141AF Figure 3.10 (2a). Pattern Generation Control Register (PG01CR) 104 TOSHIBA CORPORATION TMP96C141AF Figure 3.10 (2b). Pattern Generation Control Register (PG01CR) TOSHIBA CORPORATION 105 TMP96C141AF 7 PG0REG (004CH) bit Symbol Read/Write After reset Function Prohibit Read modify write 0 PG03 6 PG02 W 0 5 PG01 0 4 PG00 0 3 SA03 2 SA02 R/W Undefined 1 SA01 0 SA00 Pattern Generation 0 (PG0) output latch register (Reading the P6 that is set to the PG port allows to read-out.) Shift alternate register 0 For the PG mode (4-bit write) register Figure 3.10 (3). Pattern Generation 0 Register (PG0REG) 7 PG1REG (004DH) bit Symbol Read/Write After reset Function Prohibit Read modify write 0 PG13 6 PG12 W 0 5 PG11 0 4 PG10 0 3 SA13 2 SA12 R/W Undefined 1 SA11 0 SA10 Pattern Generation 1 (PG1) output latch register (Reading the P6 that is set to the PG port allows to read-out.) Shift alternate register 1 For the PG mode (4-bit write) register Figure 3.10 (4). Pattern Generation 1 Register (PG1REG) 106 TOSHIBA CORPORATION TMP96C141AF Figure 3.10 (5). 16-bit Timer Trigger Control Register (T45CR) TOSHIBA CORPORATION 107 TMP96C141AF Figure 3.10 (6). Connection of Timer and Pattern Generator (1) Pattern Generation Mode PG functions as a pattern generation according to the setting of PG01CR In this mode, set PG01CR Example of pattern generation mode 108 TOSHIBA CORPORATION TMP96C141AF Shift due to the shift trigger from timer Figure 3.10 (7). Pattern Generation Mode Block Diagram (PG0) In this pattern generation mode, only writing the output latch is disabled by hardware, but other functions do the same operation as 1-2 excitation in stepping motor control port mode. Accordingly, the data shifted by trigger signal from a timer must be written before the next trigger signal is output. TOSHIBA CORPORATION 109 TMP96C141AF (2) Stepping Motor Control Mode 4-phase 1-Step/2-Step Excitation Figure 3.10 (8) and Figure 3.10 (9) show the output waveforms of 4-phase 1 excitation and 4-phase 2 excitation, respectively when channel 0 (PG0) is selected. Initial value of PG0REG 0100 x x x x Note: bn indicates the initial value of PG0REG b7 b6 b5 b4 x x x x Normal Rotation Initial value of PG0REG 0100 x x x x Reverse Rotation Figure 3.10 (8). Output Waveforms of 4-Phase 1-Step Excitation (Normal Rotation and Reverse Rotation) 110 TOSHIBA CORPORATION TMP96C141AF Initial value of PG0REG 0100 x x x x Figure 3.10 (9). Output Waveforms of 4-Phase 2-Step Excitation (Normal Rotation) The operation when channel 0 is selected is explained below. The output latch of PG0 (also used as P6) is shifted at the rising edge of the trigger signal from the timer to be output to the port. The direction of shift is specified by PG01CR 1-step excitation will be selected when only one bit is set to "1" during the initialization of PG, while 4-phase 2-step excitation will be selected when two consecutive bits are set to "1". The value in the shift alternate registers are ignored when the 4-phase 1-step/2-step excitation mode is selected. Figure 3.10 (10) shows the block diagram. Figure 3.10 (10). Block Diagram of 4-Phase 1-Step Excitation/2-Step Excitation (Normal Rotation) TOSHIBA CORPORATION 111 TMP96C141AF 4-Phase 1-2 Step Excitation Figure 3.10 (11) shows the output waveforms of 4phase 1 -2 step excitation when channel 0 is selected. Initial value of PG0REG 11001000 Note: bn denotes the initial value of PG0REG b7 b6 b5 b4 b3 b2 b1 b0 Normal Rotation Initial value of PG0REG 10001100 Reverse Rotation Figure 3.10 (11). Output Waveforms of 4-Phase 1-2 Step Excitation (Normal Rotation and Reverse Rotation) 112 TOSHIBA CORPORATION TMP96C141AF The initialization for 4-phase 1-2 step excitation is as follows: By rearranging the initial value "b7 b6 b5 b4 b3 b2 b1 b0" to "b7 b3 b6 b2 b5 b1 b4 b0", the consecutive 3 bits are set to "1" and other bits are set to "0" (positive logic). For example, if b7, b3, and b6 are set to "1", the initial value becomes "11001000", obtaining the output waveforms as shown in Figure 3.10 (11). To get an output waveform of negative logic, set values 1s and 0's of the initial value should be inverted. For example, to change the output waveform shown in Figure 3.10 (11) into negative logic, change the initial value to "00110111". The operation will be explained below for channel 0. The output latch of PG0 (shared by P6) and the shifter alternate register (SA0) for Pattern Generation are shifted at the rising edge of trigger signal from the timer to be output to the port. The direction of shift is set by PG01CR Figure 3.10 (12). Block Diagram of 4-Phase 1-2 Step Excitation (Normal Rotation) TOSHIBA CORPORATION 113 TMP96C141AF Setting example: To drive channel 0 (PG0) by 4-phase 1-2 step excitation (normal rotation) when timer 0 is selected, set each register as follows: 7 TRUN TMOD TFFCR TREG0 P6CR P6FC - 0 x * - - - 1 1 6 x 0 x * - - - 1 - 5 - x x * - - - 0 - 4 - x 0 * - - - 0 - 3 - - 1 * 1 1 0 1 - 2 - - 0 * 1 1 0 0 - 1 - 0 1 * 1 1 1 0 - 0 0 1 0 * 1 1 1 0 1 Stop timer 0, and clears it to zero. Set 8-bit timer mode and selects T1 as the input clock of timer 0. Clear TFF1 to zero and enables the inversion trigger by timer 0. Set the cycle in timer register. Set P60 ~ P63 bits to the output mode. Set P60 ~ P63 bits to the PG output. Select PG0 4-phase 1 - 2 step excitation mode and normal rotation. Set an initial value. Start timer 0. PG01CR PG0REG TRUN Note: x; don't care -; no change (3) Trigger Signal From Timer The trigger signal from the timer which is used by PG is not equal to the trigger signal of timer flip-flop (TFF1, TFF4, TFF5, and TFF6) and differs as shown in Table 3.10 (1) depending on the operation mode of the timer. Table 3.10 (1) Select of Trigger Signal TFF1 Inversion 8-bit timer mode 16-bit timer mode PPG output mode PWM output mode Note: PG Shift Selected by TFFCR To shift PG, TFFCR Channel 1 of PG can be synchronized with the 16-bit timer Timer 4/Timer 5. In this case, the PG shift trigger signal from the 16-bit timer is output only when the up-counter UC4/ UC5 value matches TREG5/TREG7. When using a trigger signal from Timer 4, set either T4FFCR 114 TOSHIBA CORPORATION TMP96C141AF (4) Application of PG and Timer Output As explained in "Trigger signal from timer", the timing to shift PG and invert TFF differs depending on the mode of timer. An application to operate PG while operating an 8-bit timer in PPG mode will be explained below. To drive a stepping motor, in addition to the value of each phase (PG output), synchronizing signal is often required at the timing when excitation is changed over. In this application, port 6 is used as a stepping motor control port to output a synchronizing signal to the TO1 pin (shared by P71). Figure 3.10 (13). Output Waveforms of 4-Phase 1-Step Excitation Setting example: 7 TRUN TMOD TFFCR TREG0 TREG1 P7CR P7FC P6CR P6FC - 1 x * * x x - - - * 1 6 - 0 x * * x x - - - * x 5 - x x * * x x - - - * - 4 - x 0 * * x x - - - * - 3 - x 0 * * - - 1 1 0 * - 2 - x 1 * * - - 1 1 0 * - 1 0 0 1 * * 1 1 1 1 0 * 1 0 0 1 x * * - x 1 1 1 * 1 Stop timer 0, and clears it to zero. Set timer 0 and timer 1 in PPG output mode and selects T1 as the input clock. Enable TFF1 inversion and sets TFF1 to "1". Set the duty of TO1 to TREG0. Set the cycle of TO1 to TREG1. ) Assign P71 as TO1. ) Assign P60 - 63 as PG0. Set PG0 in 4-phase 1-step excitation mode. Set an initial value. Start timer 0 and timer 1. PG01CR PG0REG TRUN Note: x; don't care -; no change TOSHIBA CORPORATION 115 TMP96C141AF 3.11 Serial Channel The TMP96C141AF contains two serial I/O channels for full duplex asynchronous transmission (UART) as well as for I/O extension. The serial channel has the following operation modes: q I/O interface mode (channel 1 only) Note: TMP96C141AF/TMP96C041AF/ TMP96CM40F/TMP96PM40F with Channel 0 and 1. Mode 0: To transmit and receive I/O data as well as the synchronizing signal SCLK for extending I/O. q Asynchronous transmission (UART) mode (channel 0 and 1) Mode 1: 7-bit data Mode 2: 8-bit data Mode 3: 9-bit data In mode 1 and mode 2, a parity bit can be added. Mode 3 has wake-up function for making the master controller start slave controllers in serial link (multi-controller system). Figure 3.11 (1) shows the data format (for one frame) in each mode. When bit 8 = 1, address (select code) is denoted. When bit 8 = 0, data is denoted. Figure 3.11 (1). Data Formats 116 TOSHIBA CORPORATION TMP96C141AF The serial channel has a buffer register for transmitting and receiving operations, in order to temporarily store transmitted or received data, so that transmitting and receiving operations can be done independently (full duplex). However, in I/O interface mode, SCLK (serial clock) pin is used for both transmission and receiving, the channel becomes half-duplex. The receiving data register is of a double buffer structure to prevent the occurrence of overrun error and provides one frame of margin before CPU reads the received data. The receiving data register stores the already received data while the buffer register receives the next frame data. By using CTS and RTS (there is no RTS pin, so any one port must be controlled by software), it is possible to halt data send until CPU finishes reading receive data every time a frame is received (Handshake function). In the UART mode, a check function is added not to start the receiving operation by error start bits due to noise. The channel starts receiving data only when the start bit is detected to be normal at least twice in three samplings. When the transmission buffer becomes empty and requests the CPU to send the next transmission data, or when data is stored in the receiving data register and the CPU is requested to read the data, INTTX or INTRX interrupt occurs. Besides, if an overrun error, parity error, or framing error occurs during receiving operation, flag SC0CR/SC1CR TOSHIBA CORPORATION 117 TMP96C141AF Note: There is SC1MOD (56H) in Channel 1 Figure 3.11 (2). Serial Mode Control Register (Channel 0, SC0MOD) 118 TOSHIBA CORPORATION TMP96C141AF Note: Serial control register for channel 1 is SC1CR (55H). As all error flags are cleared after reading, do not test only a single bit with a bit-testing instruction. Figure 3.11 (3). Serial Control Register (Channel, SC0CR) TOSHIBA CORPORATION 119 TMP96C141AF Note: As all error flags are cleared after reading, do not test only a single bit with a bit-testing instruction. Figure 3.11 (4). Serial Channel Control (Channel 0, BR0CR) 7 TB7 6 TB6 6 RB6 5 TB5 5 RB5 4 TB4 4 RB4 3 TB3 3 RB3 2 TB2 2 RB2 1 TB1 1 RB1 0 TB0 0 RB0 (Transmission) SC0BUF (50H) 7 RB7 (Receiving) Figure 3.11 (5). Serial Transmission/Receiving Buffer Registers (Channel 0, SC0BUF) 120 TOSHIBA CORPORATION TMP96C141AF Figure 3.11 (6). Serial Mode Control Register (Channel 1, SC1MOD) TOSHIBA CORPORATION 121 TMP96C141AF Note: As all error flags are cleared after reading, do not test only a single bit with a bit-testing instruction. Figure 3.11 (7). Serial Control Register (Channel 1, SC1CR) 122 TOSHIBA CORPORATION TMP96C141AF Note: To use baud rate generator, set TRUN Figure 3.11 (8). Baud Rate Generator Control Register (Channel 0, BR0CR) 7 TB7 6 TB6 6 RB6 5 TB5 5 RB5 4 TB4 4 RB4 3 TB3 3 RB3 2 TB2 2 RB2 1 TB1 1 RB1 0 TB0 0 RB0 (Transmission) SC1BUF (0054H) 7 RB7 (Receiving) Figure 3.11 (9). Serial Transmission/Receiving Buffer Registers (Channel 1, SC1BUF) TOSHIBA CORPORATION 123 TMP96C141AF Figure 3.11 (10). Port 9 Function Register (P9FC) Port 3.11 (11). Port 9 Open Drain Enable Register (ODE) 124 TOSHIBA CORPORATION TMP96C141AF 3.11.2 Configuration Figure 3.11 (12) shows the block diagram of the serial channel 0. Figure 3.11 (12). Block Diagram of the Serial Channel 0 TOSHIBA CORPORATION 125 TMP96C141AF Figure 3.11 (13) shows the block diagram of the serial channel 1. Figure 3.11 (13). Block Diagram of the Serial Channel 1 126 TOSHIBA CORPORATION TMP96C141AF Baud Rate Generator Baud rate generator comprises a circuit that generates transmission and receiving clocks to determine the transfer rate of the serial channel. The input clock to the baud rate generator, T0 (fc/ 4), T2 (fc/16), T8 (fc/64), or T32 (fc/256) is generated by the 9-bit prescaler which is shared by the timers. One q of these input clocks is selected by the baud rate generator control register BR0CR/BR1CR UART mode Transfer rate = Input clock of baud rate generator / 16 Frequency divisor of baud rate generator q I/O interface mode Transfer rate = Input clock of baud rate generator /2 Frequency divisor of baud rate generator The relation between the input clock and the source clock (fc) is as follows: T0 = fc/4 T2 = fc/16 T8 = fc/64 T32 = fc/256 Accordingly, when source clock fc is 12.288 MHz, input clock is T2 (fc/16), and frequency divisor is 5, the transfer rate in UART mode becomes as follows: Transfer rate = fc/16 / 16 5 = 12.288 x 106/16/5/16 = 9600 (bps) Table 3.11 (1) shows an example of the transfer rate in UART mode. Also with 8-bit timer 0, the serial channel can get a transfer rate. Table 3.11 (2) shows an example of baud rate using timer 0. Table 3.11 (1) Selection of Transfer Rate (1) (When Baud Rate Generator is Used) Unit (kbps) Input Clock fc [Mhz] Frequency Divisor 2 4 8 0 5 A 3 6 C T0 (fc/4) 76.800 38.400 19.200 9.600 38.400 19.200 76.800 38.400 19.200 T2 (fc/16) 19.200 9.600 4.800 2.400 9.600 4.800 19.200 9.600 4.800 T8 (fc/64) 4.800 2.400 1.200 0.600 2.400 1.200 4.800 2.400 1.200 T32 (fc/256) 1.200 0.600 0.300 0.150 0.600 0.300 1.200 0.600 0.300 9.830400 12.288000 14.745600 Note: Transfer rate in I/O interface mode is 8 times as fast as the values given in the above table. TOSHIBA CORPORATION 127 TMP96C141AF Table 3.11 (2) Selection of Transfer Rate (1) (When Timer 0 (Input Clock T1) is Used) Unit (Kbps) fc TREG0 1H 2H 3H 4H 5H 8H AH 10H 14H 12.288MHz 96 48 32 24 19.2 12 9.6 6 4.8 4.8 9.6 31.25 19.2 12MHz 9.8304MHz 76.8 38.4 8MHz 62.5 31.25 6.144MHz 48 24 16 12 9.6 6 4.8 3 2.4 How to calculate the transfer rate (when timer 0 is used): Transfer rate = fc TREG0 x 8 x 16 (When timer 0 (input clock T1) is used) Input clock of timer 0 T1 = fc/8 T4 = fc/32 T16 = fc/128 Note: Timer 0 match detect signal cannot be used as the transfer clock in I/O interface mode. Serial Clock Generation Circuit This circuit generates the basic clock for transmitting and receiving data. 1) I/O interface mode (channel 1 only) When in SCLK output mode with the setting of SC1CR Receiving Counter The receiving counter is a 4-bit binary counter used in asynchronous communication (UART) mode and counts up by SIOCLK clock. Sixteen pulses of SIOCLK are used for receiving one bit of data, and the data bit is sampled three times at 7th, 8th and 9th clock. With the three samples, the received data is evaluated by the rule of majority. For example, if the sampled data bit is "1", "0" and "1" at 7th, 8th and 9th clock respectively, the received data is evaluated as "1". The sampled data "0", "0" and "1" is evaluated that the received data is "0". Receiving Control 1) I/O interface mode (channel 1 only) When in SCLK1 output mode with the setting of SC1CR TOSHIBA CORPORATION 128 TMP96C141AF 2) Asynchronous Communication (UART) mode The receiving control has a circuit for detecting the start bit by the rule of majority. When two or more "0" are detected during 3 samples, it is recognized as start bit and the receiving operation is started. Data being received is also evaluated by the rule of majority. Receiving Buffer the receiving buffer 1. However, unless the receiving buffer 2 (SC0BUF/SC1BUF) is read before all bits of the next data are received by the receiving buffer 1, an overrun error occurs. If an overrun error occurs, the contents of the receiving buffer 1 will be lost, although the contents of the receiving buffer 2 and SC0CR To prevent overrun error, the receiving buffer has a double buffer structure. Received data is stored one bit by one bit in the receiving buffer 1 (shift register type). When 7 bits or 8 bits of data are stored in the receiving buffer 1, the stored data is transferred to another receiving buffer 2 (SC0BUF/ SC1BUF), generating an interrupt INTRX0/INTRX1. The CPU reads only receiving buffer 2 (SC0BUF/SC1BUF). Even before the CPU reads the receiving buffer 2 (SC0BUF/SC1BUF), the received data can be stored in Figure 3.11 (14). Generation of Transmission Clock Transmission Controller 1) I/O interface mode (channel 1 only) In SCLK output mode with the setting of SC1CR pin at the rising edge or falling edge of SCLK input according to the setting of SC1CR TOSHIBA CORPORATION 129 TMP96C141AF Handshake function Serial channel 0 has a CTS0 pin. Using this pin, data can be sent in units of one frame; thus, overrun errors can be avoided. The handshake function is enabled/disabled by SC0MOD Figure 3.11 (15). Handshake Function Note 1: If the CTS signal falls during transmission, the next data is not sent after the completion of the current transmission. Note 2: Transmission starts at the first TxDCLK clock fall after the CTS signal falls. Figure 3.11 (16). Timing of CTS (Clear to Send) 130 TOSHIBA CORPORATION TMP96C141AF Transmission Buffer Transmission buffer (SC0BUF/SC1BUF) shifts to and sends the transmission data written from the CPU from the least significant bit (LSB) in order, using transmission shift clock TxDSFT which is generated by the transmission control. When all bits are shifted out, the transmission buffer becomes empty and generates INTTX0/ INTTX1 interrupt. Parity Control Circuit When serial channel control register SC0CR 11 Generating Timing 1) UART mode Receiving Mode Interrupt timing Framing error timing Parity error timing Overrun error timing Note: 9-Bit Center of last bit (Bit 8) Center of stop bit Center of last bit (Bit 8) Center of last bit (Bit 8) 8-Bit + Parity Center of last bit (parity bit) Center of stop bit Center of last bit (parity bit) Center of last bit (parity bit) 8-Bit, 7-Bit + Parity, 7-Bit Center of stop bit Center of stop bit Center of stop bit Center of stop bit Framing error occurs after an interrupt has occurred. Therefore, to check for framing error during interrupt operation, it is necessary to wait for 1 bit period of transfer rate. Transmitting Mode Interrupt timing 9-Bit Just before last bit is transmitted. 8-Bit + Parity 8-Bit, 7-Bit + Parity, 7-Bit TOSHIBA CORPORATION 131 TMP96C141AF 2) I/O Interface mode SCLK output mode Transmission interrupt timing SCLK input mode SCLK output mode Receiving interrupt timing SCLK input mode Immediately after rise of last SCLK signal (See Figure 3.11 (19) ). Immediately after rise of last SCLK signal (rising mode), or immediately after fall in falling mode (See Figure 3.11 (20)). Timing used to transfer received data to data receive buffer 2 (SC1BUF); that is, immediately after last SCLK (See Figure 3.11 (21)). Timing used to transfer received data to data receive buffer 2 (SC1BUF); that is, immediately after SCLK (See Figure 3.11 (22)). 3.11.3 Operational Description (1) Mode 0 (I/O interface mode) This mode is used to increase the number of I/O pins for transmitting or receiving data to or from the external shifter register. This mode includes SCLK output mode to output synchronous clock SCLK and SCLK input mode to input external synchronous clock SCLK. Figure 3.11 (17). Example of SCLK Output Mode Connection FIgure 3.11 (18). Example of SCLK Input Mode Connection 132 TOSHIBA CORPORATION TMP96C141AF Transmission In SCLK output mode, 8-bit data and synchronous clock are output from TxD pin and SCLK pin, respectively, each time the CPU writes data in the transmission buffer. When all data is output, INTES1 Figure 3.11 (19) Transmitting Operation in I/O Interface Mode (SCLK Output Mode) In SCLK output mode, 8-bit data are output from TxD1 pin when SCLK input becomes active while data are written in the transmission buffer by CPU. When all data are output, INTES1 Figure 3.11 (20). Transmitting Operation in I/O Interface Mode (SCLK Input Mode) TOSHIBA CORPORATION 133 TMP96C141AF Receiving In SCLK output mode, synchronous clock is output from SCLK pin and the data is shifted in the receiving buffer 1 whenever the receive interrupt flag INTES1 Figure 3.11 (21). Receiving Operation in I/O Interface Mode (SCLK Output Mode) In SCLK input mode, the data is shifted in the receiving buffer 1 when SCLK input becomes active, while the receive interrupt flag INTES1 data will be shifted in the receiving buffer 2 (SC1BUF) at the timing shown below, and INTES1 Figure 3.11 (22). Receiving Operation in I/O Interface Mode (SCLK Input Mode) Note: For data receiving, the system must be placed in the receive enable state (SCMOD 134 TOSHIBA CORPORATION TMP96C141AF (2) Mode 1 (7-bit UART Mode) The 7-bit mode can be set by setting serial channel mode register SC0MOD Direction of transmission (transmission rate: 2400 bps @ fc = 12.288MHz) 7 P9CR P9FC SC0MOD SC0CR BR0CR TRUN INTES0 SC0BUF Note: 6 x x 0 1 x x 1 * 5 - - - 1 1 - 0 * 4 - x x x 0 - 0 * 3 - - 0 x 0 - - * 2 - x 1 x 1 - - * 1 - x 0 0 0 - - * 0 1 1 1 0 1 - - * x x x x 0 1 1 * ) Select P90 as the TxD pin. Set 7-bit UART mode. Add an even parity. Set transfer rate at 2400 bps. Start the prescaler for the baud rate generator. Enable INTTX0 interrupt and sets interrupt level 4. Set data for transmission. x; don't care -; no change (3) Mode 2 (8-bit UART Mode) The 8-bit UART mode can be specified by setting SC0MOD SC1CR Direction of transmission (transmission rate: 9600 bps @ fc = 12.288MHz) TOSHIBA CORPORATION 135 TMP96C141AF Main setting 7 P9CR SC0MOD SC0CR BR0CR TRUN INTES0 x - x 0 1 - 6 x 0 0 x x - 5 - 1 1 0 - - 4 - x x 1 - - 3 - 1 x 0 - 1 2 - 0 x 1 - 1 1 0 0 0 0 - 0 0 - 1 0 1 - 0 Select P91 (RxD) as the input pin. Enable receiving in 8-bit UART mode. Add an odd parity. Set transfer rate at 9600 bps. Start the prescaler for the baud rate generator. Enable INTTX0 interrupt and sets interrupt level 4. Interrupt processing Acc SC0CR and 00011100 If Acc 0 then ERROR Acc SC0BUF Note: x; don't care -; no change ) Check for error. Read the received data. (4) Mode 3 (9-bit UART Mode) The 9-bit UART mode can be specified by setting SC0MOD Wake-up function In 9-bit UART mode, the wake-up function of slave controllers is enabled by setting SC0MOD . Note: TxD pin of the slave controllers must be in open drain output mode. Figure 3.11 (23). Serial Link Using Wake-Up Function 136 TOSHIBA CORPORATION TMP96C141AF Protocol Select the 9-bit UART mode for master and slave controllers. The master controller transmits one-frame data including the 8-bit select code for the slave controllers. The MSB (bit 8) Set SC0MOD Each slave controller receives the above frame, and clears WU bit to "0" if the above select code matches its own select code. The master controller transmits data to the specified slave controller whose SC0MOD The other slave controllers (with the The slave controllers (WU = 0) can transmit data to the master controller, and it is possible to indicate the end of data receiving to the master controller by this transmission. TOSHIBA CORPORATION 137 TMP96C141AF Setting Example: To link two slave controllers serially with the master controller, and use the internal clock 1 (fc/2) as the transfer clock. Since serial channels 0 and 1 operate in exactly the same * Setting the master controller Main setting P9CR P9FC INTES0 SC0MOD SC0BUF x x 1 1 0 x x 1 0 0 - - 0 1 0 - x 0 0 0 - - 1 1 0 - x 1 1 0 0 x 0 1 0 1 1 1 0 1 way, channel 0 is used for the purposes of explanation. ) Select P90 as TxD pin and P91 as RxD pin. Enable INTTX0 and sets the interrupt level 4. Enable INTRX0 and sets the interrupt level 5. Set 1 (fc/2) as the transmission clock in 9-bit UART mode. Set the select code for slave controller 1. INTTX0 interrupt SC0MOD SC0BUF - * 0 * - * - * - * - * - * - * Set TB8 to "0". Set data for transmission. * Setting the slave controller 2 Main setting P9CR P9FC ODE INTES0 SC0MOD x x x 1 0 x x x 1 0 - - x 0 1 - x x 1 1 - - x 1 1 - x x 1 1 0 x - 1 1 1 1 1 0 0 Enable INTRX0 and INTTX0. Set ) Select P91 as RxD pin and P90 as TxD pin (open drain output). INTRX0 interrupt Acc SC0BUF If Acc = Select Code Then SC0MOD4 138 - - - 0 - - - - Clear TOSHIBA CORPORATION TMP96C141AF 3.12 Analog/Digital Converter The TMP96C141AF contains a high-speed analog/digital converter (A/D converter) with 4-channel analog input that features 10-bit successive approximation. Figure 3.12 (1) shows the block diagram of the A/D converter. The 4-channel analog input pins (AN3 to AN0) are shared by input-only P5 and so can be used as input port. Figure 3.12 (1). Block Diagram of A/D Converter Note: This A/D converter does not have a built-in sample and hold circuit. Therefore, when A/D converting high-frequency signals, connect a sample and hold circuit externally. TOSHIBA CORPORATION 139 TMP96C141AF Figure 3.12 (2). A/D Control Register 140 TOSHIBA CORPORATION TMP96C141AF 7 ADREG0L (0060H) bit Symbol Read/Write After reset Function Undefined ADR01 6 ADR00 5 4 3 2 1 0 R 1 1 1 1 1 1 Lower 2 bits of A/D result for AN0 are stored. 7 ADREG0H bit Symbol (0061H) Read/Write After reset Function ADR09 6 ADR08 5 ADR07 4 ADR06 R Undefined 3 ADR05 2 ADR04 1 ADR03 0 ADR02 Upper 8 bits of A/D result for AN0 are stored. 7 ADREG1L bit Symbol (0062H) Read/Write After reset Function ADR11 Undefined 6 ADR10 5 4 3 2 1 0 R 1 1 1 1 1 1 Lower 2 bits of A/D result for AN1 are stored. 7 ADREG1H bit Symbol (0063H) Read/Write After reset Function ADR19 6 ADR18 5 ADR17 4 ADR16 R Undefined 3 ADR15 2 ADR14 1 ADR13 0 ADR12 Upper 8 bits of A/D result for AN1 are stored. Figure 3.12 (3-1). A/D Conversion Result Register (ADREG0, 1) TOSHIBA CORPORATION 141 TMP96C141AF 7 ADREG2L (0064H) bit Symbol Read/Write After reset Function Undefined ADR21 6 ADR20 5 4 3 2 1 0 R 1 1 1 1 1 1 Lower 2 bits of A/D result for AN2 are stored. 7 ADREG2H (0065H) bit Symbol Read/Write After reset Function ADR29 6 ADR28 5 ADR27 4 ADR26 R Undefined 3 ADR25 2 ADR24 1 ADR23 0 ADR22 Upper 8 bits of A/D result for AN2 are stored. 7 ADREG3L bit Symbol (0066H) Read/Write After reset Function ADR31 Undefined 6 ADR30 5 4 3 2 1 0 R 1 1 1 1 1 1 Lower 2 bits of A/D result for AN3 are stored. 7 ADREG3H bit Symbol (0067H) Read/Write After reset Function ADR39 6 ADR38 5 ADR37 4 ADR36 R Undefined 3 ADR35 2 ADR34 1 ADR33 0 ADR32 Upper 8 bits of A/D result for AN3 are stored. Figure 3.12 (3-2). A/D Conversion Result Register (ADREG2, 3) 142 TOSHIBA CORPORATION TMP96C141AF 3.12.1 Operation (1) Analog Reference Voltage High analog reference voltage is applied to the VREF pin, and low analog reference voltage is applied to AGND pin. The reference voltage between VREG and AGND is divided by 1024 using ladder resistance, and compared with the analog input voltage for A/D conversion. (2) Analog Input Channels Analog input channel is selected by ADMOD TOSHIBA CORPORATION 143 TMP96C141AF Main setting INTE0AD ADMOD 1 x 1 x 0 0 0 0 - 0 - 1 - 1 - 1 Enable INTAD and sets interrupt level 4. Specify AN3 pin as an analog input channel and starts A/D conversion in high speed mode. INTAD routine WA WA (00FF10H) INTE0AD ADMOD Note: > ADREG3 > WA 1 x 0 x 0 1 - 1 - 0 - 1 - 1 - 0 6 Read ADREG3L and ADREG3H values and writes to WA (16 bit). Right-shifts WA six times and writes 0 in upper bits. Writes contents of WA in memory at FF10H. Disable INTAD. Start the A/D conversion of analog input channels AN0 ~ AN2 in the high-speed scan repeat mode. When the analog input voltage of AN0 ~ AN2 pins is A/D converted in high speed conversion channel scan repeat mode. x; don't care -; no change 3.13 Watchdog Timer (Runaway Detecting Timer) The TMP96C141AF is containing watchdog timer of Runaway detecting. The watchdog timer (WDT) is used to return the CPU to the normal state when it detects that the CPU has started to malfunction (runaway) due to causes such as noise. When the watchdog timer detects a malfunction, it generates a nonmaskable interrupt to notify the CPU of the malfunction, and outputs 0 externally from watchdog timer out pin WDTOUT to notify the peripheral devices of the malfunction. Connecting the watchdog timer output to the reset pin internally forces a reset. 144 TOSHIBA CORPORATION TMP96C141AF 3.13.1 Configuration Figure 3.13 (1) shows the block diagram of the watchdog timer (WDT). Figure 3.13 (1). Block Diagram of Watchdog Timer TOSHIBA CORPORATION 145 TMP96C141AF The watchdog timer is a 22-stage binary counter which uses (fc/2) as the input clock. There are four outputs from the binary counter: 216/fc, 218/fc, 220/fc, and 222/fc. Selecting one of the outputs with the WDMOD register generates a watchdog interrupt, and outputs watchdog timer out when an overflow occurs. Since the watchdog timer out pin (WDTOUT) outputs "0" due to a watchdog timer overflow, the peripheral devices can be reset. The watchdog timer out pin is set to 1 by clearing the watchdog timer (by writing a clear code 4EH in the WDCR register). In other words, the WDTOUT keeps outputting "0" until the clear code is written. The watchdog timer out pin can also be connected to the reset pin internally. In this case, the watchdog timer out pin (WDTOUT) outputs 0 at 8 to 20 states (800ns to 2s @ 20MHz) and resets itself. Figure 3.13 (2). Normal Mode Figure 3.13 (3). Reset Mode 146 TOSHIBA CORPORATION TMP96C141AF 3.13.2 Control Registers Watchdog timer WDT is controlled by two control registers WDMOD and WDCR. (1) Watchdog Timer Mode Register (WDMOD) Setting the detecting time of watchdog timer * Disable control WDMOD WDCR 0 1 - 0 - 1 - 1 - 0 - 0 x 0 x 1 Clear WDMOD * Enable control Set WDMOD counting by writing clear code (4EH) into the WDCR register. WDCR 0 1 0 0 1 1 1 0 Write the clear code (4EH). TOSHIBA CORPORATION 147 TMP96C141AF Figure 3.13 (4). Watchdog Timer Mode Register 148 TOSHIBA CORPORATION TMP96C141AF Figure 3.13 (5). Watchdog Timer Control Register TOSHIBA CORPORATION 149 TMP96C141AF 3.13.3 Operation The watchdog timer generates interrupt INTWD after the detecting time set in the WDMOD Example: Clear the binary counter WDCR 0 1 0 0 1 1 1 0 Write clear code (4EH). Set the watchdog timer detecting time to 218/fc WDMOD 1 0 1 - - - x x Disable the watchdog timer WDMOD WDCR 0 1 - 0 - 1 - 1 - 0 - 0 x 0 x 1 Clear WDTE to "0". Write disable code (B1H). Set IDLE mode WDMOD WDCR 0 1 - 0 - 1 - 1 1 0 0 0 x 0 x 1 Set the standby mode Disables WDT and sets IDLE mode. Executes HALT command Set the STOP mode (warming up time: 216/fc) WDMOD - - - 1 0 1 x x Set the STOP mode. Execute HALT instruction. Set the standby mode. Executes HALT command 150 TOSHIBA CORPORATION TMP96C141AF 4. Electrical Characteristics 4.1 Absolute Maximum (TMP96C141AF) Symbol Vcc V IN IOL IOH PD T SOLDER T STG T OPR Parameter Power Supply Voltage Input Voltage Output Current (total) Output Current (total) Power Dissipation (Ta = 70C) Soldering Temperature (10s) Storage Temperature Operating Temperature Rating -0.5 ~ 6.5 -0.5 ~ Vcc + 0.5 100 -100 600 260 -65 ~ 150 -20 ~ 70 Unit V V mA mA mW C C C 4.2 DC Characteristics (TMP96C141AF) Vcc = 5V 10%, Ta = -20 ~ 70C (Typical values are for Ta = 25C and Vcc = 5V) Symbol V IL V IL1 V IL2 V IL3 V IL4 V IH V IH1 V IH2 V IH3 V IH4 V OL V OH V OH1 V OH2 I DAR I LI I LO Darlington Drive Current (8 Output Pins max.) Input Leakage Current Output Leakage Current Operating Current (RUN) IDLE STOP (Ta = -20 ~ 70C) STOP (Ta = 0 ~ 50C) Power Down Voltage (@STOP, RAM Back up) RESET Pull Up Register Pin Capacitance Schmitt Width RESET, NMI, INTO (P87) Pull Down/Up Register I-DAR is guaranteed for a total of up to 8 ports. Parameter Input Low Voltage (AD0-15) P2, P3, P4, P5, P6, P7, P8, P9 RESET, NMI, INTO (P87) EA X1 Input High Voltage (AD0-15) P2, P3, P4, P5, P6, P7, P8, P9 RESET, NMI, INTO (P87) EA X1 Output Low Voltage Output High Voltage Min -0.3 -0.3 -0.3 -0.3 -0.3 2.2 0.7Vcc 0.75Vcc Vcc - 0.3 0.8Vcc 2.4 0.75Vcc 0.9Vcc -1.0 0.02 (Typ) 0.05 (Typ) 26 (Typ) 1.7 (Typ) 0.2 (Typ) 2.0 50 Max 0.8 0.3Vcc 0.25Vcc 0.3 0.2Vcc Vcc + 0.3 Vcc + 0.3 Vcc + 0.3 Vcc + 0.3 Vcc + 0.3 0.45 Unit V V V V V V V V V V V V V V I OL = 1.6mA I OH = -400A I OH = -100A I OH = - 20A V EXT - 1.5V R EXT = 1.1K 0.0 Vin Vcc Test Condition -3.5 5 10 50 10 50 10 6.0 150 10 mA A A mA mA A A V K pF V K 0.2 Vin Vcc - 0.2 t osc = 16MHz 0.2 Vin Vcc - 0.2 0.2 Vin Vcc - 0.2 V IL2 = 0.2Vcc, V IH2 = 0.8Vcc tosc = 1MHz I cc V STOP R RST C IO V TH RK Note: 0.4 50 1.0 (Typ) 150 TOSHIBA CORPORATION 151 TMP96C141AF 4.3 AC Electrical Characteristics (TMP96C141AF) Vcc = 5V10%, Ta = -20 ~ 70C (4MHz ~ 20MHz) Variable No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Symbol tOSC tCLK tAK tKA tAL tLA tLL tLC tCL tACL tACH tCA tADL tADH tRD tRR tHR tRAE tWW tDW tWD tAEH tAWL tCW tAPH tAPH2 tCP tASRH tASRL tRAC tRAH tRAS tRP tRSH tRSC tRCD tCAC tCAS Osc. Period (= x) CLK width A0 - 23 ValidCLK Hold CLK ValidA0 - 23 Hold A0-15 ValidALE fall ALE fallA0 - 15 Hold ALE High width ALE fallRD/WR fall RD/WR riseALE rise A0 - 15 ValidRD/WR fall A0 - 23 ValidRD/WR fall RD/WR riseA0 - 23 Hold A0 - 15 ValidD0 - 15 input A0 - 23 ValidD0 - 15 input RD fallD0 - 15 input RD Low width RD riseD0 - 15 Hold RD riseA0 - 15 output WR Low width D0 - 15 ValidWR rise WR riseD0 - 15 Hold A0 - 23 ValidWAIT input (1WAIT + n mode) A0 - 15 ValidWAIT input (1WAIT + n mode) RD/WR fallWAIT Hold (1WAIT + n mode) A0 - 23 ValidPORT input A0 - 23 ValidPORT Hold WR risePORT Valid A0 - 23 ValidRAS fall A0 - 15 ValidRAS fall RAS fallD0 - 15 input RAS fallA0 - 15 Hold RAS Low width RAS High width CAS fallRAS rise RAS riseCAS rise RAS fallCAS fall CAS fallD0 - 15 input CAS Low width 1.5x - 30 0.5x - 15 2.0x - 40 2.0x - 40 1.0x - 35 0.5x - 25 1.0x - 40 1.5x - 65 64.0 1.0x - 40 0.5x - 15 2.5x - 70 16.0 85.0 85.0 28.0 6.0 23.0 29 40.0 2.5x + 50 200 23.0 16.0 130 10.0 60.0 60.0 15.0 0.0 100 10 2.0x + 0 2.5x - 120 206.0 200 10.0 10.0 86 2.0x - 40 0 x - 15 2.0x - 40 2.0x - 50 0.5x - 10 3.5x - 90 3.0x - 80 125.0 80 175.0 200 Parameter Min 50 2x - 40 0.5x - 20 1.5x - 70 0.5x - 15 0.5x - 15 x - 40 0.5x - 30 0.5x - 20 x - 25 1.5x - 50 0.5x - 20 3.0x - 45 3.5x - 65 2.0x - 50 85.0 0.0 48.0 85.0 75.0 21.0 129 108 100.0 36 Max 250 Min 62.5 85 11.0 240 160 160 23.0 1.0 11.0 38.0 44.0 11.0 143 154 75 60.0 0.0 35.0 60.0 50.0 15.0 85 70 Max Min 50 60.0 50 50 100 100 100 -5 50 250 25.0 5 105 110 50 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 16MHz 20MHz Unit AC Measuring Conditions * Output Level: High 2.2V (However CL = 100pF for AD0 ~ * Input Level: High 2.4V High 0.8Vcc /Low 0.8V, CL50pF AD15, AD0 ~ AD23, ALE, RD, WR, HWR, R/W, CLK, RAS, CAS0 ~ CAS2) /Low 0.45V (AD0 ~ AD15) /Low 0.2Vcc (Except for AD0 ~ AD15) 152 TOSHIBA CORPORATION TMP96C141AF (1) Read Cycle TOSHIBA CORPORATION 153 TMP96C141AF (2) Write Cycle 154 TOSHIBA CORPORATION TMP96C141AF 4.4 A/D Conversion Characteristics (TMP96C141AF) Vcc = 5V10% TA = -20 ~ 70C Symbol VREF AGND VAIN IREF Parameter Analog reference voltage Analog reference voltage Analog input voltage range Analog current for analog reference voltage Low speed conversion mode Error 4 fc (Quantize error of 0.5 LSB not included) 16 fc 16MHz High speed conversion mode Low speed conversion mode 20MHz High speed conversion mode Min Vcc - 1.5 Vss Vss 0.5 1.5 (TBD) 3.0 (TBD) 1.5 (TBD) 4.0 (TBD) Typ Vcc Vss Max Vcc Vss Vcc 1.5 4.0 6.0 LSB 4.0 8.0 mA V Unit 4.5 Serial Channel Timing - I/O Interface Mode Vcc = 5V10% TA = -20 ~ 70C (1) SCLK Input Mode Variable Symbol tSCY tOSS tOHS tHSR tSRD SCLK cycle Output Datarising edge of SCLK SCLK rising edgeoutput data hold SCLK rising edgeinput data hold SCLK rising edgeeffective data input Parameter Min 16x tSCY/2 - 5x - 50 5x - 100 0 tSCY - 5x - 100 Max Min 1 137 212 0 587 Max Min 0.8 100 150 0 450 Max s ns ns ns ns 16MHz 20MHz Unit (2) SCLK Output Mode Variable Symbol tSCY tOSS tOHS tHSR tSRD Parameter Min SCLK cycle (programmable) Output Datarising edge of SCLK SCLK rising edgeoutput data hold SCLK rising edgeinput data hold SCLK rising edgeeffective data input 16x tSCY - 2x - 150 2x - 80 0 tSCY - 2x - 150 Max 8192x Min 1 725 45 0 725 Max 512 Min 0.8 550 20 0 550 Max 409.6 s ns ns ns ns 16MHz 20MHz Unit 4.6 Timer/Counter Input Clock (TI0, TI4, TI5, TI6, TI7) Vcc = 5V10% TA = -20 ~ 70C Variable Symbol tVCK tVCKL tVCKH Clock cycle Low level clock pulse width High level clock pulse width Parameter Min 8x + 100 4x + 40 4x + 40 Max Min 600 290 290 Max Min 500 240 240 Max ns ns ns 16MHz 20MHz Unit TOSHIBA CORPORATION 155 TMP96C141AF 4.7 Interrupt Operation Vcc = 5V10% Ta = -20 ~ 70C Variable Symbol tINTAL tINTAH tINTBL tINTBH Parameter Min NMI, INT0 Low level pulse width NMI, INT0 High level pulse width INT4 ~ INT7 Low level pulse width INT4 ~ INT7 High level pulse width 4x 4x 8x + 100 8x + 100 Max Min 250 250 600 600 Max Min 200 200 500 500 Max ns ns ns ns 16MHz 20MHz Unit 156 TOSHIBA CORPORATION TMP96C141AF 4.8 Timing Chart for I/O Interface Mode TOSHIBA CORPORATION 157 TMP96C141AF 4.9 Timing Chart for Bus Request (BUSRQ)/BUS Acknowledge (BUSAK) Variable Symbol tBRC tCBAL tCBAH tABA tBAA Parameter Min BUSRQ setup time for CLK CLKBUSAK falling edge CLKBUSAK rising edge Output buffer is off to BUSAK BUSAK output buffer is on. 0 0 120 1.5x + 120 0.5x + 40 80 80 0 0 Max 16MHz Min 120 214 71 80 80 0 0 Max 20MHz Unit Min 120 195 65 80 80 Max ns ns ns ns ns Note 1: The Bus will be released after the WAIT request is inactive, when the BUSRQ is set to "0" during "Wait" cycle. Note 2: This line only shows the output buffer is off-states. They don't indicate the signal levels are fixed. After the bus is released, the signal level is kept dynamically before the bus is released by the external capacitance. Therefore, to fix the signal level by an external resistance under the bus is releasing, the design must be carefully because of the level-fix will be delayed. The internal programmable pull-up/pull-down resistance is switched active by the internal signal. 158 TOSHIBA CORPORATION TMP96C141AF 4.10 Interrupt Operation Vcc = 5V, Ta = -25C, unless otherwise noted TOSHIBA CORPORATION 159 TMP96C141AF 5. Table of Special Function Registers (SFRs) (SFR; Special Function Register) The special function registers (SFRs) include the I/O ports and peripheral control registers allocated to the 128-byte addresses from 000000H to 00007FH. (1) (2) (3) (4) (5) (6) (7) (8) (9) I/O port I/O port control Timer control Pattern Generator control Watch Dog Timer control Serial Channel control A/D converter control Interrupt control Chip Select/Wait Control Configuration of the table 160 TOSHIBA CORPORATION TMP96C141AF Table 5 I/O Register Address Map Address 000000H P0 1H P1 2H P0CR 3H 4H P1CR 5H P1FC 6H P2 7H P3 8H P2CR 9H P2FC AH P3CR BH P3FC CH P4 DH P5 EH P4CR FH 10H P4FC 11H 12H P6 13H P7 14H P6CR 15H P7CR 16H P6FC 17H P7FC 18H P8 19H P9 1AH P8CR 1BH P9CR 1CH P8FC 1DH P9FC 1EH 1FH Name Address 20H TRUN 21H 22H TREG0 23H TREG1 24H TMOD 25H TFFCR 26H TREG2 27H TREG3 28H P0MOD 29H P1MOD 2AH PFFCR 2BH 2CH 2DH 2EH 2FH 30H TREG4L 31H TREG4H 32H TREG5L 33H TREG5H 34H CAP1L 35H CAP1H 36H CAP2L 37H CAP2H 38H T4MOD 39H TFF4CR 3AH T45CR 3BH 3CH 3DH 3EH 3FH Name Address Name Address 60H ADREG0L 61H ADREG0H 62H ADREG1L 63H ADREG1H 64H ADREG2L 65H ADREG2H 66H ADREG3L 67H ADREG3H 68H B0CS 69H B1CS 6AH B2CS 6BH 6CH 6DH 6EH 6FH 70H INTE0AD 71H INTE45 72H INTE67 73H INTET10 74H INTEPW10 75H INTET54 76H INTET76 77H INTES0 78H INTES1 79H 7AH 7BH IIMC 7CH DMA0V 7DH DMA1V 7EH DMA2V 7FH DMA3V Name 40H TREG6L 41H TREG6H 42H TREG7L 43H TREG7H 44H CAP3L 45H CAP3H 46H CAP4L 47H CAP4H 48H T5MOD 49H T5FFCR 4AH 4BH 4CH PG0REG 4DH PG1REG 4EH PG01CR 4FH 50H SC0BUF 51H SC0CR 52H SC0MOD 53H BR0CR 54H SC1BUF 55H SC1CR 56H SC1MOD 57H BR1CR 58H ODE 59H 5AH 5BH 5CH WDMOD 5DH WDCR 5EH ADMOD 5FH TOSHIBA CORPORATION 161 TMP96C141AF (1) I/O Port Symbol Name Address 7 P07 P0 PORT0 00H 6 P06 5 P05 4 P04 R/W Input mode Undefined P17 P1 PORT1 01H 0 P27 P2 PORT2 06H 0 P37 P3 PORT3 07H 1 1 1 0 P36 0 P35 Input mode 1 1 1 P42 P4 PORT4 0CH 0 P53 P5 PORT5 0DH P67 P6 PORT6 12H 1 1 1 1 P66 P65 P64 R/W Input mode 1 P73 P7 PORT7 13H 1 P87 P8 PORT8 18H 1 1 1 P95 P9 PORT9 19H 1 Note: 3 P03 2 P02 1 P01 0 P00 P16 P15 P14 R/W Input mode P13 P12 P11 P10 0 P26 0 P25 0 P24 R/W Input mode 0 P34 R/W 0 P23 0 P22 0 P21 0 P20 0 P33 0 P32 0 P31 0 P30 Output mode 1 P41 R/W Input mode 1 P51 R Input mode P63 P62 P61 P60 1 P50 P52 1 P40 1 P72 R/W Input mode 1 P82 1 P71 1 P70 1 P81 1 P80 P86 P85 P84 R/W Input mode 1 P94 P83 1 P93 R/W Input mode 1 P92 1 P91 1 P90 1 1 1 1 1 When P30 pin is defined as RD signal output mode (P30F = 1), clearing the output latch register P30 to "0" outputs the RD strobe from P30 pin for PSRAM, even when the internal address is accessed. If the output latch register P30 remains "1", the RD strobe is output only when the external address is accessed. Read/Write R/W ; Either read or write is possible R ; Only read is possible W ; Only write is possible Prohibit RWM ; Prohibit Read Modify Write. (Prohibit RES/SET/TSET/CHG/STCF/ANDCF/ORCF/XORCF Instruction) TOSHIBA CORPORATION 162 TMP96C141AF (2) I/O Port Control (1/2) Symbol Name Address 02H (Prohibit RMW) 7 P07C P0CR PORT0 Control 0 P17C P1CR PORT1 Control 04H (Prohibit RMW) 0 P27F P1FC PORT1 Function 05H (Prohibit RMW) 0 P27C P2CR PORT2 Control 08H (Prohibit RMW) 0 P27F P2FC PORT2 Function 09H (Prohibit RMW) 0 P37C P3CR PORT3 Control 0AH (Prohibit RMW) 0 P37F P3FC PORT3 Function 0BH (Prohibit RMW) 0 O : PORT 1 : RAS 6 P06C 0 P16C 0 P26F 0 P26C 0 P26F 0 P36C 0 P36F 0 O : PORT 1 : R/W 5 P05C 0 P15C 0 P25F 0 P25C 0 P25F 0 P35C W 0 P35F 0 O : PORT 1 : BUSAK 0 0 : IN 1 : OUT P34F W 0 O : PORT 1 : BUSRQ 0 O : PORT 1 : HWR P42C P4CR PORT4 Control 0EH (Prohibit RMW) 0 P42F P4FC PORT4 Function 10H (Prohibit RMW) 0 0 O : PORT 1 : WR P41C W 0 0 : IN 1 : OUT P41F W 0 0 : PORT 1 : CS/CAS Note: With the TMP96C141A/TMP96C141A/TMP96C041A, which requires an external ROM, PORT0 functions as AD0 to AD7; PORT1, AD8 to AD15; P30, the RD signal; P31, the WR signal, regardless of the values set in P0CR, P1CR, P1FC, P30F and P31F. 4 P04C W 0 P14C W 0 P24F W 0 P24C W 0 P24F W 0 P34C 3 P03C 0 P13C 0 P23F 0 P23C 0 P23F 0 P33C 0 2 P02C 0 P12C 0 P22F 0 P22C 0 P22F 0 P32C 0 P32F 1 P01C 0 P11C 0 P21F 0 P21C 0 P21F 0 0 P00C 0 P10C 0 P20F 0 P20C 0 P20F 0 0 : IN 1 : OUT (When external access, set as AD7 - 0 and cleared to "0".) < P1FC/ P1CR = 00 : IN, 01 : OUT, 10 : AD15 - 8, 11 : A23 - 16 < P2FC/ P2CR = 00 : IN, 01 : OUT, 10 : A7 - 0, 11 : A23 - 16 P31F P30F 0 O : PORT 1 : RD P40C 0 P40F 0 TOSHIBA CORPORATION 163 TMP96C141AF I/O Port Control (2/2) Symbol Name Address 14H (Prohibit RMW) 7 P67C P6CR PORT6 Control 0 6 P66C 0 5 P65C 0 4 P64C W 0 0 : IN 1 : OUT P73C P7CR PORT7 Control 15H (Prohibit RMW) P67F P6FC PORT6 Function 16H (Prohibit RMW) 0 P66F 0 P65F 0 P64F W 0 0 P73F P7FC PORT7 Function 17H (Prohibit RMW) 0 0 : PORT 1 : TO3 P87C P8CR PORT8 Control 1AH (Prohibit RMW) 0 P86C 0 P85C 0 P95C P9CR PORT9 Control 1BH (Prohibit RMW) P86F P8FC PORT8 Function 1CH (Prohibit RMW) W 0 0 : PORT 1 : TO6 P95F P9FC PORT9 Function 1DH (Prohibit RMW) W 0 0 : PORT 1 : SCLK1 0 P84C W 0 0 : IN 1 : OUT P94C 0 P93C W 0 0:IN 1:OUT P83F W 0 0 : PORT 1 : TO5 P93F W 0 0 : PORT 1 : TxD1 P82F W 0 0 : PORT 1 : TO4 P92F W 0 0 : PORT 1 : SCLK0 P90F W 0 0 : PORT 1 : TxD0 0 0 0 P92C P91C P90C 0 0 0 0 P83C 0 P72F W 0 0 :PORT 1 : TO2 P82C 0 0 : PORT 1 : TO1 P81C P80C 0 P71F 0 0 : PORT 1 : PG1 - OUT 0 : PORT 1 : PGO - OUT 0 P63F P72C W 0 0 : IN 1 : OUT P62F P61F P60F 0 0 P71C P70C 0 0 0 0 3 P63C 2 P62C 1 P61C 0 P60C 164 TOSHIBA CORPORATION TMP96C141AF (3) Timer Control (1/4) Symbol Name Address 7 PRRUN R/W TRUN Timer Control 20H 0 0 0 0 6 5 T5RUN 4 T4RUN 3 P1RUN R/W 0 0 0 Prescaler and Timer Run/Stop CONTROL 0 : Stop and Clear 1 : Run (Count up) 22H (Prohibit RMW) 23H (Prohibit RMW) T10M1 8bit Timer Source CLK and MODE 24H (Prohibit RMW) 0 T10M0 0 PWMM1 0 00 : - 01 : 26 - 1 10 : 27 - 1 11 : 28 - 1 - W Undefined - W Undefined PWMM0 W 0 PWM 0 00 : TO0TRG 01 : T1 10 : T16 11 : T256 TFF1C1 W 0 00 : Invert TFF1 01 : Set TFF1 10 : Clear TFF1 11 : Don't care - TREG2 PWM Timer Register 2 26H (R)/W (Can read double buffer values.) Undefined - TREG3 PWM Timer Register 3 27H FF2RD R P0MOD PWM0 MODE 28H (Prohibit RMW) - TFF2 output value 0 1 : Double Buffer Enable 0 0 : Overflow Interrupt 1: Compare/ Match Interrupt PWM1INT 0 0 0 : PWM Mode 1 : Timer Mode PWM1M 0 DB2EN (R)/W (Can read double buffer values.) Undefined PWM0INT PWM0M T2CLK1 W 0 0 0 00 : 26 - 1 01 : 27 - 1 10 : 28 - 1 11 : Don't care PWM1S1 0 00 : 26 - 1 01 : 27 - 1 10:28 - 1 11:Don't care PWM1S0 0 0 00 : P1(fc/4) 01 : P4(fc/16) 10 : P16(fc/64) 11 : Don't care T3CLK1 W 0 1 : Double Buffer Enable 0 0 0 : Overflow 0 : PWM Mode Interrupt 1 : Compare/ 1 : Timer Mode Match Interrupt 00 : P1(fc/4) 01 : P4(fc/16) 10 : P16(fc/64) 11 : Don't care T3CLK0 T2CLK0 PWM0S1 PWM0S0 0 0 1 : TFF1 Invert Enable TFF1C0 0 0 00 : TI0 Input 01 : T1 10 : T4 11:T16 TFF1IE R/W 0 0 : Inverted by Timer 0 TFF1IS 0 00 : 8-bit Timer 01 : 16-bit Timer 10 : 8-bit PPG 11 : 8-bit PWM T1CLK1 T1CLK0 T0CLK1 T0CLK0 2 P0RUN 1 T1RUN 0 T0RUN TREG0 8bit Timer Register 0 TREG1 8bit Timer Register 1 TMOD DBEN R/W TFFCR 8bit Timer Flip-flop Control 0 25H 1 : Double Buffer Enable FF3RD R P1MOD PWM1 MODE 29H (Prohibit RMW) - TFF3 output value DB3EN TOSHIBA CORPORATION 165 TMP96C141AF Timer Control (2/4) Symbol Name Address 7 FF3C1 W 0 PFFCR PWM Flip-flop Control 2AH 00 : Don't care 01 : Set TFF3 10 : Clear TFF3 11 : Don't care 0 0 6 FF3C0 5 FF3TRG1 R/W 0 0 00 : Don't care 01 : Set TFF2 10 : Clear TFF2 11 : Don't care 00 : Prohibit TFF3 Inverted 01 : Invert if matched 10 : Set if matched; Clear if overflowed 11 : Clear if matched; set if overflowed - W Undefined - W Undefined - W Undefined - W Undefined - CAP1L Capture Register 1L 34H R Undefined - CAP1H Capture Register 1H 35H R Undefined - CAP2L Capture Register 2L 36H R Undefined - CAP2H Capture Register 2H 37H CAP2T5 R/W T4MOD 16-bit Timer 4 Source CLK and MODE 0 38H TFF5 INV TRG O: TRG Disable 1: TRG Enable 0 EQ5T5 CAP1IN W 0 0 : SoftCapture 1 : Don't care 0 0 Capture Timing 00 : Disable 01 : T14 T15 10 : T14 T14 11 : TFF1 TFF1 CAP12M1 R Undefined CAP12M0 R/W 0 1 : UC4 Clear Enable 0 Source Clock 00 : TI4 01 : T1 10 : T4 11 :T16 0 CLE T4CLK1 T4CLK0 4 FF3TRG0 3 FF2C1 W 0 0 2 FF2C0 1 FF2TRG1 R/W 0 00 : Prohibit TFF2 Inverted 01 : Invert if matched 10 : Set if matched; Clear if overflowed 11 : Clear if matched; set if overflowed 0 FF2TRG0 TREG4L 16-bit Timer Register 4L 30H (Prohibit RMW) 31H (Prohibit RMW) 32H (Prohibit RMW) 33H (Prohibit RMW) TREG4H 16-bit Timer Register 4H TREG5L 16-bit Timer Register 5L TREG5H 16-bit Timer Register 5H 166 TOSHIBA CORPORATION TMP96C141AF Timer Control (3/4) Symbol Name Address 7 TFF5C1 16bit Timer 4 Flip-flop Control W 39H 0 00 : Invert TFF5 01 : Set TFF5 10 : Clear TFF5 11 : Don't care - R/W 0 T45CR T4, T5 Control 3AH Fix at "0" 0 PG1 shift trigger 0 : Timer 0, 1 1 : Timer 5 - W Undefined - W Undefined - W Undefined - W Undefined - CAP3L Capture Register 3L 44H R Undefined - CAP3H Capture Register 3H 45H R Undefined - CAP4L Capture Register 4L 46H R Undefined - CAP4H Capture Register 4H 47H CAP3IN R/W T5MOD 16bit Timer 5 Source CLK and MODE 0 48H 0 : SoftCapture 1 : Don't care 0 0 0 0 0 1 : UC5 Clear Enable 0 Capture Timing 00 : Disable 01 : T16 T17 10 : T16 T16 11 : TFF1 TFF1 CAP34M1 R Undefined CAP34M0 CLE T5CLK1 W 0 Source Clock 00 : Invert TFF6 01 : Set TFF6 10 : Clear TFF6 11 : Don't care 167 T5CLK0 0 PG0 shift trigger O : Timer 0, 1 1 : Timer 4 0 0 0 TFF4 Invert Trigger 0 : Trigger Disable 1 : Trigger Enable 6 TFF5C0 5 CAP2T4 4 CAP1T4 R/W 0 0 0 3 EQ5T4 2 EQ4T4 1 TFF4C1 W 0 Source Clock 00 : Invert TFF4 01 : Set TFF4 10 : Clear TFF4 11 : Don't care PG0T R/W 0 1 : Double Buffer Enable 0 DB6EN DB4EN 0 TFF4C0 T4FFCR PG1T TREG6L 16bit Timer Register 6L 40H (Prohibit RMW) 41H (Prohibit RMW) 42H (Prohibit RMW) 43H (Prohibit RMW) TREG6H 16bit Timer Register 6H TREG7L 16bit Timer Register 7L TREG7H 16bit Timer Register 7H TOSHIBA CORPORATION TMP96C141AF Timer Control (4/4) Symbol Name Address 7 6 5 CAP4T6 R/W T5FFCR 16bit Timer 5 Flip-flop Control 0 49H TFF6 Invert Trigger 0 : Trigger Disable 1 : Trigger Enable 0 0 0 0 4 CAP3T6 3 EQ7T6 2 EQ6T6 1 TFF6C1 W 0 00 : Invert TFF6 01 : Set TFF6 10 : Clear TFF6 11 : Don't care 0 TFF6C0 (4) Pattern Generator Symbol Name Address 4CH (Prohibit RMW) 4DH (Prohibit RMW) 7 PG03 0 PG13 0 PAT1 4EH (Prohibit RMW) 0 0 : 8bit write 1 : 4bit write 6 PG02 W 0 PG12 W 0 CCW1 0 0 : Normal Rotation 1 : Reverse Rotation 0 PG1M 0 0 : 4bit Step 1 : 8bit Step 0 PG1TE R/W 0 PG1 trigger input enable 1 : Enable 0 0 : 8bit write 1 : 4bit write 0 0 : Normal Rotation 1 : Reverse Rotation 0 0 : 4bit Step 1 : 8bit Step 0 PG0 trigger input enable 1 : Enable PG01CR PG0, 1 Control PAT0 CCW0 0 PG11 0 PG10 SA13 SA12 R/W Undefined PG0M PG0TE 5 PG01 4 PG00 3 SA03 2 SA02 R/W Undefined SA11 SA10 1 SA01 0 SA00 PG0REG PGO Register PG1REG PG1 Register (5) Watch Dog Timer Symbol Name Address 7 WDTE 1 WDMOD Watch Dog Timer Mode 5CH 1 : WDT Enable 6 WDTP1 0 00 : 216/fc 01 : 218/fc 10 : 220/fc 11 : 222/fc 5 WDTP0 0 4 WARM R/W 0 Warming up Time 0 : 214/fc 1 : 216/fc - 5DH W - B1H : WDT Disable Code 4EH : WDT Clear Code 0 0 0 1 : Connect internally WDT out pin to Reset Pin 0 1 : Drive the pin in STOP Mode Standby Mode 00 : RUN Mode 01 : STOP Mode 10 : IDLE Mode 11 : Don't care 3 HALTM1 2 HALTM0 1 RESCR 0 DRVE WDCR Watch Dog Timer Control Register 168 TOSHIBA CORPORATION TMP96C141AF (6) Serial Channel (1/2) Symbol Name Serial Channel 0 Buffer Address 7 RB7 TB7 50H 6 RB6 TB6 5 RB5 TB5 4 RB4 TB4 Undefined RB8 R SC0CR Serial Channel 0 Control 0 51H Receiving data bit 8 Parity 0 : Odd 1 : Even CTSE 0 1 : Parity Enable Overrun WU R/W SC0MOD Serial Channel 0 Mode 0 52H Transmission 1 : CTS data bit 8 Enable - R/W BR0CR Baud Rate Control 0 53H Fix at "0" 0 0 00 : t0 (fc/4) 01 : t2 (fc/16) 10 : t8 (fc/64) 11 :t32 (fc/256) RB6 TB6 RB5 TB5 RB4 TB4 Undefined RB8 R 0 SC1CR Serial Channel 1 Control 55H Receiving data bit 8 Parity 0 : Odd 1 : Even 1 : Parity Enable Overrun EVEN R/W 0 0 PE OERR PERR 0 1 : Error 1 : Input SCLK1 pin FERR 0 SCLKS R/W 0 0 IOC R (Cleared to 0 by reading) RB3 TB3 1 : Receive Enable BR0CK1 1 : Wake up Enable BR0CK0 0 0 0 0 00 : Unused 01 : UART 7bit 10 : UART 8bit 11 : UART 9bit BR053 R/W 0 0 0 0 BR052 0 0 00 : TO0 Trigger 01 : Baud rate generator 10 : Internal clock 1 11 : Don't care BR051 BR050 0 EVEN R/W 0 0 PE OERR PERR 0 1 : Error Parity SM1 Framing SM0 SC1 1: Input SCLK0 pin (Note) SC0 FERR 0 - R/W 0 0 - R (Cleared to 0 by reading) 3 RB3 TB3 2 RB2 TB2 1 RB1 TB1 0 RB0 TB0 SC0BUF R (Receiving)/W (Transmission) TB8 RXE Set frequency divisor 0~F ("1" prohibited) RB2 TB2 RB1 TB1 RB0 TB0 SC1BUF Serial Channel 1 Buffer RB7 TB7 54H R (Receiving)/W (Transmission) Parity Framing TB8 Serial Channel 1 Mode 0 56H Transmission data bit 8 - 0 RXE 0 1 : Receive Enable WU R/W 0 1 : Wake up Enable SM1 0 SM0 0 SC1 0 SC0 0 SC1MOD Fix at "0" 00 : I/O Interface 01 : UART 7bit 10 : UART 8-bit 11 : UART 9bit 00 : TO0 Trigger 01 : Baud rate generator 10 : Internal clock 1 11 : Don't care TOSHIBA CORPORATION 169 TMP96C141AF Serial Channel (2/2) Symbol Name Address 7 - R/W BR1CR Baud Rate Control 0 57H Fix at "0" 0 0 00 : t0 (fc/4) 01 : t2 (fc/16) 10 : t8 (fc/64) 11 :t32 (fc/256) 6 5 BR1CK1 4 BR1CK0 3 BR153 R/W 0 0 0 0 2 BR152 1 BR151 0 BR150 Set frequency divisor 0~F ("1" prohibited) ODE1 R/W 0 1 : P93 Open-drain ODE0 0 1 : P90 Open-drain - ODE Special Open Drain Enable 58H (7) A/D Converter Control Symbol Name Address 7 EOCF ADMOD A/D Converter Mode reg R 5EH 0 1 : End *1) AD REG0L ADR01 AD Result Reg 0 low 60H Undefined ADR09 AD REG0H *1) AD REG1L AD Result Reg 0 high 61H ADR11 AD Result Reg 1 low 62H Undefined ADR19 AD REG1H *1) AD REG2L AD Result Reg 1 high 63H ADR21 AD Result Reg 2 low 64H Undefined ADR29 AD REG2H *1) AD REG3L AD REG3H *1: 6 ADBF 0 1: Busy ADR00 5 REPET 0 1 : Repeat mode 4 SCAN 0 1 : Scan mode R 3 ADCS R/W 0 1 : Slow mode 2 ADS 0 1 : START 1 ADCH1 0 0 ADCH0 0 Analog Input Channel Series 1 ADR07 1 ADR06 R Undefined 1 ADR05 1 ADR04 1 ADR03 1 ADR02 ADR08 ADR10 R 1 ADR17 1 ADR16 R Undefined ADR20 R 1 ADR27 1 ADR26 R Undefined 1 ADR25 1 ADR24 1 ADR23 1 ADR22 ADR28 1 ADR15 1 ADR14 1 ADR13 1 ADR12 ADR18 AD Result Reg 2 high 65H ADR31 ADR30 AD Result Reg 3 low 66H Undefined ADR39 ADR38 1 ADR37 1 ADR36 R 1 ADR35 R Undefined 1 ADR34 1 ADR33 1 ADR32 AD Result Reg 3 high 67H Data to be stored in A/D Conversion Result Reg Low are the lower 2 bits of the conversion result. The contents of the lower 6 bits of this register are always read as "1". TOSHIBA CORPORATION 170 TMP96C141AF (8) Interrupt Control (1/2) TOSHIBA CORPORATION 171 TMP96C141AF Interrupt Control (2/2) Symbol Name DMA 0 request Vector Address 7CH (Prohibit RMW) 7 6 5 4 3 2 DMA0 start vector DMA0V DMA0V8 0 DMA 1 request Vector 7DH (Prohibit RMW) DMA01V8 0 DMA 2 request Vector 7EH (Prohibit RMW) DMA2V8 0 DMA 3 request Vector 7FH (Prohibit RMW) DMA3V8 0 DMA0V7 0 DMA1V7 0 DMA2V7 0 DMA3V7 0 DMA0V6 W 0 DMA1 start vector DMA1V DMA1V6 W 0 DMA2 start vector DMA2V DMA2V6 W 0 DMA3 start vector DMA3V DMA3V6 W 0 I0IE W 0 IIMC Interrupt Input Mode Control 7BH (Prohibit RMW) 0 I0LE W 0 0 : INTO edge mode 1 : INTO level mode 0 NMIREE W 0 1 : Operate even at NMI rise edge DAM3V5 DMA3V4 0 0 DAM2V5 DMA2V4 0 0 DAM1V5 DMA1V4 0 0 DAM0V5 DMA0V4 1 0 1 : INT0 input enable 172 TOSHIBA CORPORATION TMP96C141AF (9) Chip Select/Wait Controller Symbol Name Address 7 B0E Block 0 CS/WAIT control register W 68H (Prohibit RMW) 0 1 : CS Enable B1E Block 1 CS/WAIT control register W 69H (Prohibit RMW) 0 1 : CS Enable B2E Block 2 CS/WAIT control register W 6AH (Prohibit RMW) 0 1 : CS Enable 6 B0SYS W 0 1 : SYSTEM only B1SYS W 0 1 : SYSTEM only B2SYS W 0 1 : SYSTEM only 5 B0CAS W 0 0 : CS0 1 : CAS0 B1CAS W 0 0 : CS1 1 : CAS1 B2CAS W 0 0 : CS2 1 : CAS2 4 B0BUS W 0 0 : 16bit Bus 1 : 8bit Bus B1BUS W 0 0 : 16bit Bus 1 : 8bit Bus B2BUS W 0 0 : 16bit Bus 1 : 8bit Bus 3 B0W1 W 0 2 B0W0 W 0 00 : 2WAIT 01 : 1WAIT 10 : 1WAIT + n 11 : 0WAIT B1W1 W 0 B1W0 W 0 00 : 2WAIT 01 : 1WAIT 10 : 1WAIT + n 11 : 0WAIT B2W1 W 0 B2W0 W 0 00 : 2WAIT 01 : 1WAIT 10 : 1WAIT + n 11 : 0WAIT 1 B0C1 W 0 0 B0C0 W 0 B0CS 00 : 7F00H ~ 7FFFH 01 : 400000H ~ 10 : 800000H ~ 11 : C00000H ~ B1C1 W 0 B1C0 W 0 B1CS 00 : 480H ~ 7FFFH 01 : 400000H ~ 10 : 800000H ~ 11 : C00000H ~ B2C1 W 0 00 : 8000H ~ 01 : 400000H ~ 10 : 800000H ~ 11 : C00000H ~ B2C0 W 0 B2CS Note 1: After reset, only "Block 2" is set to enable. After reset, the program starts in 16-bit data bus, 2-wait state. Note 2: These registers can be accessed only in system mode. Note 3: TMP96C141A for internal RAM less is 80H ~ 7FFFH. TOSHIBA CORPORATION 173 TMP96C141AF 6. Port Section Equivalent Circuit Diagram * Reading The Circuit Diagram Basically, the gate singles written are the same as those used for the standard CMOS logic IC [74HCXX] series. The dedicated signal is described below. STOP: This signal becomes active "1" when the hold mode setting register is set to the STOP mode and the CPU executes the HALT instruction. When the drive enable bit [DRIVE] is set to "1", however, STP remains at "0". * The input protection resistor ranges from several tens of ohms to several hundreds of ohms. * PO (AD0 ~ AD7), P1 (AD8 ~ 15, A8 ~ 15), P2 (A2 - 23, A0 ~7) * P30 (RD), P31 (WR) * P32 ~ 37, P40 ~ 41, P6, P7, P80 ~ 86, P91 ~ 92, P94 ~ 95 174 TOSHIBA CORPORATION TMP96C141AF * P42 (CS2, CAS2) * P5 (AN0 ~ 3) * P87 (INT0) * P90 (TXD0), P93 (TXD1) TOSHIBA CORPORATION 175 TMP96C141AF * NMI * WDTOUT * CLK * EA, AM8/16 * ALE * RESET 176 TOSHIBA CORPORATION TMP96C141AF * X1, X2 * VREF, AGND TOSHIBA CORPORATION 177 TMP96C141AF 7. Guidelines and Restrictions (1) Special Expression Explanation of a built-in I/O register: Register Symbol external oscillator. As a result, it takes warming up time from inputting the releasing request to outputting the system clock. High Speed DMA (DRAM) refresh mode) When the bus is released (BUSAK = "0") for waiting to accept the interrupt, DRAM refresh is not performed because of the high speed DMA is generated by an interrupt. { Programmable Pull Up/Down Resistance The programmable pull up/down resistors can be selected ON/OFF by program when they are used as the input ports. The case of they are used as the output ports, they cannot be selected ON/OFF by program. Bus Releasing Function Refer to the "Note about the Bus Release" in 3.5 Functions of Ports because the pin state when the bus is released is written. Watch Dog Timer When the bus is released, both internal memory and internal I/O cannot be accessed. But internal I/O cantinues to operate. So, the watch dog timer continues to run. Therefore, be carefull about the bus releasing time and set the detection timer of watch dog timer. ~ Watch Dog Timer The watch dog timer starts operation immediately after the reset is released. When the watch dog timer is not used, set watch dog timer to disable. CPU (High SpeedDMA) Only the "LDC cr, r", "LDC r, cr" instruction can be used to access the control register like transfer source address register (DMASn) in the CPU. 178 TOSHIBA CORPORATION |
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